• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.7
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• pp.1332-1340
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• 2007

This paper describes an efficient hardware design of key wrap/unwrap algorithm for security layer of WiBro system. The key wrap/unwrap core (WB_KeyWuW) is based on AES (Advanced Encryption Standard) algorithm, and performs encryption/decryption of 128bit TEK (Traffic Encryption Key) with 128bit KEK (Key Encryption Key). In order to achieve m area-efficient implementation, two design techniques are considered; First, round transformation block within AES core is designed using a shared structure for encryption/decryption. Secondly, SubByte/InvSubByte blocks that require the largest hardware in AES core are implemented by using field transformation technique. As a result, the gate count of the WB_KeyWuW core is reduced by about 25% compared with conventional LUT (Lookup Table)-based design. The WB_KeyWuW con designed in Verilog-HDL has about 14,300 gates, and the estimated throughput is about $16{\sim}22-Mbps$ at 100-MHz@3.3V, thus the designed core can be used as an IP for the hardware design of WiBro security system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.2
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• pp.246-252
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• 2012

STBC is a technique where a multiple antenna signals are transmitted. With this technique, antenna diversity can be achieved. The performance of STBC OFDM system using pilot symbol for the channel estimation is analyzed. IEEE 802.16e standards suggest that the BER performance of STBC system can be improved using channel state information. Pilot symbol is used for the channel estimation in OFDM systems. However, imperfect channel estimates in this systems degrade the performance. The performance of this STBC OFDM systems using channel state information, gauged by the average bit error rate, is analyzed considering the channel estimation error.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.8A
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• pp.706-711
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• 2012

Multi-level cell NAND flash is a flash memory technology using multiple levels per cell to allow more bits to be stored. Currently, most multi-level cell NAND stores 2 bits of information per cell. This reduces the amount of margin separating the states and results in the possibility of more errors. The most error cause is coupling noise. Thus, in this paper, we studied coupling noise cancellation scheme for reduction memory on the 16-level cell NAND flash memory channel. Also, we compared the performance threshold detection and proposed scheme.

• Proceedings of the Korea Information Processing Society Conference
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• 2009.04a
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• pp.1474-1477
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• 2009

본 논문에서는 ASR(Arithmetic Shift Register)과 SHA-2로 구성된 32비트 출력의 새로운 스트림 암호 ASC를 제안한다. ASC는 소프트웨어 및 하드웨어 구현이 쉽게 디자인된 스트림 암호 알고리즘이다. 특히 계산능력이 제한된 무선 통신장비에서 빠르게 수행할 수 있도록 개발되었다. ASC는 다양한 길이(8-32바이트)의 키를 지원하고 있으며, 워드 단위로 연산을 수행한다. ASC는 매우 간결한 구조를 가지고 있으며 선형 궤환 순서기(Linear Feedback Sequencer)로 ASR을 적용하였고, 비선형 순서기(Nonlinear sequencer)로 SHA-2를 적용하여 크게 두 부분으로 구성되어 있는 결합 함수(combining function) 스트림 암호이다. 그리고 8비트, 16비트, 32비트 프로세스에서 쉽게 구현이 가능하다. 제안한 스트림 암호 ASC는 최근에 표준 블록 암호로 제정된 AES, ARIA, SEED등의 블록 암호보다는 6-13배 빠른 결과를 보여주고 있으며, 안전성 또한 현대 암호 알고리즘이 필요로 하는 안전성을 만족하고 있다.

• Journal of Advanced Navigation Technology
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• v.16 no.5
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• pp.810-816
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• 2012

In this paper, BER(Bit Error Ratio) performances of the TransferJet system, which is the standard of a close proximity inductive wireless communication system, are presented and analyzed. Comparing to other wireless communication systems, the TransferJet system has some advantages such as short communication range(i.e., high security in the wireless communication environments), fewer effects of multipath distortion, and higher transmission rate. In order to demodulate the received signal, either SC(Soft-decision Combining) or HC(Hard-decision Combining) can apply to the despreader and demodulator of the receiver. When the spreading factor is more than 4, the SC scheme approximately has a minimum signal-to-noise ratio gain of 2 dB over the HC scheme. Moreover, from simulation results, we can conclude that the quantization bits of 3 bits are an optimum value for the SC scheme in the TransferJet system since the 3-bit quantization achieves nearly the performance as that attained by double-precision floating-point.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.4A
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• pp.414-422
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• 2011

This paper describes a design of low-density parity-check(LDPC) decoder supporting block length 2,304-bit and code rate 1/2 of IEEE 802.16e mobile WiMAX standard. The designed LDPC decoder employs the min-sum algorithm and partially parallel layered-decoding architecture which processes a sub-matrix of $96{\times}96$ in parallel. By exploiting the properties of the min-sum algorithm, a new memory reduction technique is proposed, which reduces check node memory by 46% compared to conventional method. Functional verification results show that it has average bit-error-rate(BER) of $4.34{\times}10^{-5}$ for AWGN channel with Fb/No=2.1dB. Our LDPC decoder synthesized with a $0.18{\mu}m$ CMOS cell library has 174,181 gates and 52,992 bits memory, and the estimated throughput is about 417 Mbps at 100-MHz@l.8-V.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.1
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• pp.29-42
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• 1990

In this paper, We use the APL as IDL when simulation a 16-bit SIP. It was possible for IDL to represent and describe a structure of a H/W which other HDL have not. Because We partitioned whole system to various modules when desingning processor, We adpoted a direct decoding method. A designed each modules are executed according to 12-bit control word was inputed through experimental framework, Which were composed to symbolized instructions. In here, By setting instruction codes of the SIP using binary code, We composed instruction format and assembler instruction, and verified the SIP behaviour that try to implement by entering a presented instruction set through experimental framework. In a presented SIP, Because inputing program are a symbolized language, Designer and user will easily understand behaviour of system. Especially, Because we can immediatly specify a unit function within SIP, We will use variously and easily the library cell.

• KIPE Magazine
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• v.9 no.3
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• pp.13-17
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• 2004

근래에 Texas Instruments(TI)사에서 개발된 TMS3320LF240x는 고정 소숫점 방식의 16비트 DSP으로써 저가, 고성능용으로 개발된 칩이다. 이 DSP는 비교적 빠른 계산속도에 다양한 입력/출력장치를 내장하고 있으므로 DSP 장점과 마이크로제어기의 장점을 모두 가지고 있다. 특히 Flash 메모리, RAM 등 메모를 포함하여 8-16채널 이상 A/D 컨버터, Timer, 직력통신과 함께 PWM인버터/컨버터용 PWM펄스까지 출력시킬 수 있으므로, 이 DSP는 각종 전동기 구동시스템과 SUP, 능동필터 제어 등 전력전자 분야에서 적합하게 설계된 DSP로 상당히 많이 사용되고 있다. 그런데 TMS320LF240x는 고정 소숫점 방식의 16비트 DSP이므로 연산량이 많은 시스템에서는 적용하기 힘들며, 또는 저장할 데이터량이 많은 제어시스템일 경우에는 내장된 flash 및 SRAM 등 메모리 용량이 부족하는 등 사용하는데 문제가 있을 가능성이 있다.(중략)

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1996.11a
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• pp.341-345
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• 1996

This paper presents the dynamics and the teal-time control of a horizontally rotating inverted pendulum. The dynamic equations representing three degrees of freedom rigid body motion of the pendulum are derived, and the state feedback controller is applied to the motion control of the pendulum. A 32 bit counter board with 16 bit hardware communication ability is developed to improve the real-time control performance and is applied to a horizontally rotating inverted pendulum. The simulation and experimental studies are conducted to evaluate the performance of the developed pendulum system and the timing in the real-time control is analyzed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.7
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• pp.663-679
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• 1991

본 논문에서는 다중 경로 페이딩 채널에서 최대 다중 경로 지연폭이 한 비트 폭보다 큰 경우 발생할 수 있는 심볼간 간섭을 극복하기 위해 M-ary 신호 방식과 절환 신호 방식을 채용한 다중 경로 다이버시티 수신 noncoherent F나 ds / SSMA 통신 시스템의 평균 오율을 평가하였다. 시스템의 평균 오율은 가우스 근사법을 이용해 채널 파라메타와 PN 시퀀스의 길이와 같은 시스템 파라메타에 대한 식으로 표현하였고, 이러한 결과식을 이용해 M-ary FSK 시스템과 두 종류의 절환 수신기에 대한 FSK시스템의 평균 오율을 수치적으로 분석하였다.