• Title/Summary/Keyword: 화소설계

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Mutual Information-based Circular Template Matching for Image Registration (영상등록을 위한 Mutual Information 기반의 원형 템플릿 정합)

  • Ye, Chul-Soo
    • Korean Journal of Remote Sensing
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    • v.30 no.5
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    • pp.547-557
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    • 2014
  • This paper presents a method for designing circular template used in similarity measurement for image registration. Circular template has translation and rotation invariant property, which results in correct matching of control points for image registration under the condition of translation and rotation between reference and sensed images. Circular template consisting of the pixels located on the multiple circumferences of the circles whose radii vary from zero to a certain distance, is converted to two-dimensional Discrete Polar Coordinate Matrix (DPCM), whose elements are the pixels of the circular template. For sensed image, the same type of circular template and DPCM are created by rotating the circular template repeatedly by a certain degree in the range between 0 and 360 degrees and then similarity is calculated using mutual information of the two DPCMs. The best match is determined when the mutual information for each rotation angle at each pixel in search area is maximum. The proposed algorithm was tested using KOMPSAT-2 images acquired at two different times and the results indicate high accurate matching performance under image rotation.

Parallel Processing of k-Means Clustering Algorithm for Unsupervised Classification of Large Satellite Images: A Hybrid Method Using Multicores and a PC-Cluster (대용량 위성영상의 무감독 분류를 위한 k-Means Clustering 알고리즘의 병렬처리: 다중코어와 PC-Cluster를 이용한 Hybrid 방식)

  • Han, Soohee;Song, Jeong Heon
    • Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
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    • v.37 no.6
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    • pp.445-452
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    • 2019
  • In this study, parallel processing codes of k-means clustering algorithm were developed and implemented in a PC-cluster for unsupervised classification of large satellite images. We implemented intra-node code using multicores of CPU (Central Processing Unit) based on OpenMP (Open Multi-Processing), inter-nodes code using a PC-cluster based on message passing interface, and hybrid code using both. The PC-cluster consists of one master node and eight slave nodes, and each node is equipped with eight multicores. Two operating systems, Microsoft Windows and Canonical Ubuntu, were installed in the PC-cluster in turn and tested to compare parallel processing performance. Two multispectral satellite images were tested, which are a medium-capacity LANDSAT 8 OLI (Operational Land Imager) image and a high-capacity Sentinel 2A image. To evaluate the performance of parallel processing, speedup and efficiency were measured. Overall, the speedup was over N / 2 and the efficiency was over 0.5. From the comparison of the two operating systems, the Ubuntu system showed two to three times faster performance. To confirm that the results of the sequential and parallel processing coincide with the other, the center value of each band and the number of classified pixels were compared, and result images were examined by pixel to pixel comparison. It was found that care should be taken to avoid false sharing of OpenMP in intra-node implementation. To process large satellite images in a PC-cluster, code and hardware should be designed to reduce performance degradation caused by file I / O. Also, it was found that performance can differ depending on the operating system installed in a PC-cluster.

Design of a Motion Adaptive LCD controller for image enlargement (영상 확대를 위한 움직임 적응형 LCD 제어기 설계)

  • 이승준;권병헌;최명렬
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.40 no.3
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    • pp.109-116
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    • 2003
  • In this paper. we Propose an UXGA class LCD controller for controlling the LCD panel. The proposed controller supports the full screen display using GCD between input and output resolutions. The proposed LCD controller includes the motion detector based on median filter which can detect the motion of input image for the enhancement of a image quality. Also, it divides the motion into 3 stages such as still, semi-moving and moving, and uses the different interpolation algorithms according to the degree of motion. In order to evaluate the performance of the proposed interpolation algorithm, we use PSNR method and compare the conventional algorithm by using computer simulation. For the proposed motion detection algorithm, we use a visual verification and the estimation of pixel changes. The proposed LCD controller has been designed and verified by VHDL. It has been synthesized using Xilinx VirtexE FPGA.

Fine Digital Sun Sensor Design and Analysis for STSAT-2 (과학기술위성 2호(STSAT-2)의 고 정밀 디지털 태양센서(FDSS) 설계 및 분석)

  • Rhee, Sung-Ho;Jang, Tae-Seong;Kim, Sae-Il;Lim, Jong-Tae
    • Journal of the Korean Society for Aeronautical & Space Sciences
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    • v.33 no.10
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    • pp.93-97
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    • 2005
  • We have developed the FDSS (Fine Digital Sun Sensor) for the space technology of the STSAT-2 (Seience & Technology Satellite 2). The FDSS is firstly developed by using CMOS image sensor(CIS) in South Korea. The FDSS consists of the optics part, FPGA(Field Programable Gate Array) part, and MCU(Micro controller unit)part. This paper will focus on the optical characteristics of the optics part and describe the configuration of FDSS with the design of aperture. We also analyze the characteristic of optics about the pixel of the CMOS image sensor.

Impulse Noise Removal Using Noise Detector and Total Variation Optimization (잡음 검출기와 총변량 최적화를 이용한 영상의 임펄스 잡음제거)

  • Lee Im-Geun
    • The Journal of the Korea Contents Association
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    • v.6 no.4
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    • pp.11-18
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    • 2006
  • A new algorithm for removing salt and pepper impulse noise in image using impulse noise detector and total variation optimization is presented. The proposed two types of noise detectors which are based on the adaptive median filter, can detect impulse noise with high accuracy while reducing the probability of detecting image details as impulses. And the detectors maintain its performance independent of noise density. For removing impulses, total variation optimization is applied only to those detected noise candidate to reduces unnecessary computation. The proposed approach successfully remove impulse noise while preserving image details.

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A Design of a Cellular Neural Network for the Real Image Processing (실영상처리를 위한 셀룰러 신경망 설계)

  • Kim Seung-Soo;Jeon Heung-Woo
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.10 no.2
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    • pp.283-290
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    • 2006
  • The cellular neural networks have the structure that consists of an array of the same cell which is a simple processing element, and each of the cells has local connectivity and space invariant template properties. So, it has a very suitable structure for the hardware implementation. But, it is impossible to have a one-to-one mapping between the CNN hardware processors and the pixels of the practical large image. In this paper, a $5{\times}5$ CNN hardware processor with pipeline input and output that can be applied to the time-multiplexing processing scheme, which processes the large image with a small CNN cell block, is designed. the operation of the implemented $5{\times}5$ CNN hardware processor is verified from the edge detection and the shadow detection experimentations.

The Development of High Resolution Film Scanner Using DSP (DSP를 이용한 고해상도 스캐너 개발)

  • 김태현;최은석;백중환
    • Proceedings of the Korea Institute of Convergence Signal Processing
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    • 2000.12a
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    • pp.149-152
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    • 2000
  • A scanner is an output device that scans documents, photographs, films etc, and convert them to digital data. Especially, a film scanner is used for scanning negative/positive films. In this paper, we design step motor control part, image sensor part, and Aか converter part which are components of the scanner and use DSP for fast signal processing. We also design the interface circuits using EPLD between these peripherals and DSP. The PC interface circuits between scanner and PC are designed by using parallel port to control and transfer the scanned data from scanner to PC. For 35mm film, we design hardwares which obtain high resolution more than 9 million pixels (horizontal resolution is 3835 and vertical resolution is 2592).

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광시야각 표준화를 선도하는 Advanced FFS 기술

  • Lee, Gyeong-Ha;Im, Yeong-Jin
    • Information Display
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    • v.5 no.5
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    • pp.4-9
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    • 2004
  • 최근 비오이 하이디스에서는 무제한의 광시야각과 시야각에 따른 색변화가 최소화된 선명한 색 특성을 갖는 Advanced FFS(Fringe Field Switching) 기술을 개발하였다. 이 기술은 resin 기술적용(평탄화에 의한 고개구율)없이 종래의 FFS 기술에서 액정의 전기 광특성을 최적화하는 새로운 디자인 룰을 찾아내어 실현하였다. 진보된 화소 개념은 전극의 모서리 구조, 전극 간격/폭, 칼라 필터의 블랙 마트릭스(BM)와 전극 간격등의 key parameters들의 최적화에 의해 달성되었고 액정 셀 내의 모서리와 전기장등이 액정을 미세하게 조정할 수 있도록 있게 된 것이다. 이러한 진보된 설계 개념은 모든 FFS 제품에 반영되어 개발되었다. 뿐만 아니라 12.1" XGA 제품에서 투과율이 22% 증가하고 흑백 대비비(Contrast Ratio)는 33% 증가한 600 : 1의 세계 최고 사양을 갖는 제품을 개발하게 되었다. 특히 태블릿과 노트북용 TFT- LCD 모듈에서 단일 도메인(Single Domain) 모드로도 White상태에서 시야각에 따른 색변화가 0.02 이하의 특성을 갖고 180도/180도의 무제한 시야각을 갖고 있다. Advanced FFS 기술의 브랜드 이름과 슬로건으로 'Viewiz'와 'Vision Magic'을 정하여 마케팅 중이며 세계적인 Top Tier 고객에 제품을 판매 중이고, 2004년 3분기에는 태블릿 시장에서 점유율 70%로 1위를 차지하였다.

Filter Design for Removal Blocking Artifacts in Low Bit-rate Video Coding (저 비트율 영상부호화의 블록화 현상 제거를 위한 Filter 설계)

  • 조용설;전병우
    • Proceedings of the IEEK Conference
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    • 2000.09a
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    • pp.403-406
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    • 2000
  • 본 논문에서는 저비트율 영상통신에서 발생되는 블록화현상과 컬러 번짐 현상을 효과적으로 줄임으로써, 주관적 화질을 개선하는 후처리 필터를 제안한다. 저비트율 영상통신에서 8*8 블록 단위의 DCT 수행은 블록화 및 컬러 번짐 현상과 같은 화질 열화를 초래한다. 이러한 화질 열화를 개선하기 위하여 밝기 영역과 컬러 영역에서 각기 다른 후처리 필터를 본 논문에서 제안한다. 밝기 부분의 후처리 필터에서는 일률적인 후처리 필터에서 발생하게 되는 새로운 artifact 인 geometric pattern 을 방지하기 위해 각 화소의 공간영역에서 블록 경계 좌우로 filtering range 를 다르게 수행하고, 컬러부분의 후처리 필터에서는 컬러번짐 현상을 최대한 억제하기 위해 블록간 컬러 값의 차이에 따라 다르게 수행되는 후처리 필터를 제안한다. 제안된 실험을 통하여 후처리 필터를 수행한 영상화질이 H.263 baseline 에 비해 월등히 나아짐을 확인할 수 있었으며, H.263 Annex J의 deblocking filter mode에 비해서도 떨어지지 않는 화질을 얻을 수 있었다.

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Special Memory Design for Graphics (그래픽스 전용 메모리 설계)

  • 김성진;문상호
    • Journal of Korea Multimedia Society
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    • v.2 no.1
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    • pp.80-88
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    • 1999
  • In this paper, we propose a Special Memory for Graphics(SMGRA) which accelerates memory access time for graphics operations. The SMGRA has a rectangular array memory architecture which has already proposed by Whelan to process pixels in the rectangle area simultaneously, but the SMGRA should improve address decoding time and reduce the number of address pins by using address multiplexing scheme. The SMGRA has a Z-value comparator in the DRAM which is to convert read-modify-write Z buffer into single-write only operation that improves approximately 50% frame buffer access bandwidth.

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