• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.13 no.10
• /
• pp.4751-4756
• /
• 2012

Blushes are known to generate unwanted nano particles of dust and harm elements in various electro-mechanical home appliances. Subsequently, the blushless type is proposed as an eco-friendly alternative to replace the brushes. Further, the expensive magnetized rotor of the Blush-less DC (BLDC) is to be replaced in SRM, which requires complex control not to overflow the switching current the system within a budget. This paper introduces an approach to implement an efficient yet, cost-effective controller for high-speed rotation control, employing Switched Reluctance Motor (SRM) BLDC motor.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.30 no.2
• /
• pp.57-64
• /
• 2016

Power demand has continuously increased with technological and economical development. The load density is also growing in the center of downtown area. In particular, underground facilities have been increased on the purpose of the prevention of urban disasters and pedestrian environment improvement. Based on this situation, the underground space in urban surroundings has gradually decreased because of the limited space. The ampacity of buried cables is affected by various factors such as cable size, soil thermal resistance, burial depth and filling material. The thermal capacity of the facilities is determined by the absorb heat surrounding the cable and the soil. The maximum operating temperature of cable is the highest temperature when the insulator of cable is not damaged in the case of high enough temperature. In this paper, the most effective cabling configuration is suggested using the duct array adjustment. It was also considered to increase the number of cable line. This underground distribution system was simulated by using ETAP(Electrical Transient Analysis Program).

• The Transactions of the Korean Institute of Electrical Engineers A
• /
• v.52 no.7
• /
• pp.414-420
• /
• 2003

The domestic needs for larger capability of power sources are increasing to cope with the expanding power load which results from the industrial developments & the progressed life style. In summer, the peak load is mainly due to the non-industrial reasons such as air-conditioners and other cooling equipments. To cover the concentrated peak load in stable, the power transmission lines should be more constructed and efficiently operated. The ampacity design of the underground cable system is generally following international standards such as IEC287, IEC60853 and JCS168 which regards the shape of 100% daily full power loads. It is not so efficient to neglect the real shapes of load curves generally below 60~70% of full load. The dynamic (real time) rating system tends to be used with the measured thermal parameters which make it possible to calculate the maximum ampacity within required periods. In this paper, the CTM(Conductor Temperature Monitoring) which is the base of dynamic rating systems for tunnel environment is proposed by a design of lumped thermal network ($\pi$-type thermal model) and distribution temperature sensor attached configuration, including the estimation results of its performances by load cycle test on 345kV single phase XLPE cable.

• Proceedings of the KIEE Conference
• /
• 2006.07d
• /
• pp.1836-1837
• /
• 2006

본 논문에서는 차량용 전자제어식 주차 브레이크(Electric Parking Brake, EPB) 시스템의 고장 허용 제어(fault tolerant control)를 위한 고장 안전 기법(fail-safe logic)을 제안한다. 고장 안전 기법의 구현을 위하여 EPB 구동 모터에 흐르는 전류 리플을 측정하여 센서리스 위치 추정을 한다. 추정값과 홀 센서의 출력을 비교하여 잔차(residual)를 발생하고, 이를 이용하여 시스템 내부의 고장을 진단하고 고장 안전 기법을 통하여 전체 시스템의 오작동을 방지한다. 시스템 오작동을 방지하기 위한 고장 안전 기법에 대하여 정의하고 모의실험을 통하여 내부 시스템의 고장이 발생 시 이 기법이 고장을 진단하고 시스템을 안전하게 운영할 수 있음을 확인하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2004.04b
• /
• pp.46-50
• /
• 2004

인쇄/소결 방법으로 가시영역에서 광감도가 매우 큰 CdSSe 다결정 후막을 만들고 이를 이용하여 광전도 젤을 제작하였다. 후막의 낱알 크기는 $5{\mu}m$ 정도이였다. 광전도 셀은 소결 촉진제로 첨가한 $cucl_2$ 양이 CdSSe 1 g 당 3.06~0.10 mg 정도이변 감도, 광전류와 암전류의 비율이 각각 0.7과 $10^5$ 이상을 나타내었고, Cds 와 CdSe 의 질량비가 1:0, 9:1, 8:2, 7:3, 6:4, 5:5일 때 응답파장은 각각 500nm, 520nm, 540nm, 570nm, 620nm, 660nm였다. 또한 주파수 특성을 나타내는 응답시간은 오름시간과 감쇠시간이 각각 30관 20ms 정도 이였으며 최대허용 소비 전력은 80mw 이상이었다. 이상과 같이 인쇄/소결 방법으로 제작된 광전도 셀은 $cucl_2$ 양이 CdSSe 1g 당 0.06~0.10 mg 정도 주입되면 센서로써 좋은 특성을 나타내었다.

• Journal of the Korean Vacuum Society
• /
• v.2 no.1
• /
• pp.73-77
• /
• 1993

Hot-wall evaporation technique으로 세라믹 기판 위에 CdS 박막을 성장하였다. 이 때 증발원과 기판의 온도는 각각 570, 40$0^{\circ}C$이고 두께는 3$mu extrm{m}$이었다. 공기 중에서 열처리하여 감도(${\gamma}$), 광전류와 암전류의 비(pc/dc), 최대허용소비전력(MAPD), spectral response 및 응답시간 등을 측정하였다. $550^{\circ}C$, 30분간 열처리한 경우 가장 좋은 광전도 특성을 얻었으며 ${\gamma}$=0.89, pc/cd~104, MAPD: 492mW, rise time이 100ms, decay time이 260ms이었다.

• Transactions of the Korean Society of Mechanical Engineers
• /
• v.13 no.4
• /
• pp.697-702
• /
• 1989

This study deals with the heat cycle characteristics of sleeve connector of aluminum stranded conductors steel reinforced(ACSR). In order to investigate the effect of heat cycle on the sleeve connector of stranded conductor, experimental study has been performed for both the temperature rising and electrical resistance of sleeve connector. Also, the effect of changes in surrounding temperature on the allowable current of sleeve connector was studied in order to investigate the influence on the connector size of conductor. Under the given test conditions of heat cycle, the temperature rising s decreased with the increase of sleeve size of conductor. The deviation of resistance of sleeve connector in conductor decreased with the increase in the size of sleeve connector.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.30 no.3
• /
• pp.53-58
• /
• 2016

The underground transmission lines which have been built to expand the suppling facilities will be continuously accompanying with high growth of the increase of power demand in the metropolitan area in recent years. So, it is necessary to maximize the ability and reliability of power supply with the current-carrying capability of the underground transmission lines. Design criteria of KEPCO is to be presented and used frequently. But it has to be studied about the installation methods of power cable buried in ground. In this study, we used the program for calculating the current-carrying capability of underground transmission power cables. We estimated the maximum permissible current values by the horizontal arrangement in the installation methods of power cable(154kV XLPE $600mm^2$) buried ducts in ground. To see the general tendency of the analysis, we researched a statistical analysis with such parameters as the maximum permissible current values. Through the regression analysis, we analyze the most highly values of the maximum permissible current on the Ra type duct arrangement.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.18 no.6
• /
• pp.91-99
• /
• 2004

Most of LV customer have applied the 3-phase four wire system distribution system because it has advantage of supplying both of 1-phase at 3-phase loads simultaneously. Due to its structural simplicity, it is more convenient for use rather than the conventional separated scheme. But once in a while uneven load unbalance or unclean power quality lead some problems such as do-rating or power losses. In this paper, voltage and current waveform in the actual fields have been measured and analyzed in relation with intermationally allowable voltage unbalance limits.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2010.02a
• /
• pp.248-248
• /
• 2010

CMOS 축소화가 32nm node를 넘어서 지속적으로 진행되기 위하여 FinFET, Surround Gate and Tri-Gate와 같은 Fully Depleted 3-Dimensional 소자들이 SCE를 다루기 위해서 많이 제안되어 왔다. 하지만 소자의 축소화를 진행함에 있어서 좁고 균일한 patterning을 형성하는 것과 동시에 낮은 Extension Region과 Contact Region에서의 Series Resistance을 제공하여야 하고 Source/Drain Contact Formation을 확보하여야 한다. 그리고 소자의 축소화가 진행됨으로써 Silicide의 응집현상과 Source/Drain Junction의 누설전류에 대한 허용범위가 점점 엄격해지고 있다. ITRS 2005에 따르면 32nm CMOS에서는 Contact Resistivity가 대략 $2{\times}10-8{\Omega}cm2$이 요구되고 있다. 또한 Three Dimensional 소자에서는 Fin Corner Effect가 Channel Region뿐만 아니라 S/D Region에서도 중대한 영향을 미치게 된다. 따라서 본 논문에서 제시하는 Novel S/D Contact Formation 기술을 이용하여 Self-Aligned Dual/Single Metal Contact을 이루어Patterning에 대한 문제점 해결과 축소화에 따라 증가하는 Contact Resistivity 문제점을 해결책을 제시하고자 한다. 이를 검증하기3D MOSFET제작하고 본 기술을 적용하고 검증한다. 또한 Normal Doping 구조를 가진3D MOSFET뿐만 아니라 SCE를 해결하기 위해서 대안으로 제시되고 있는 SB-MOSFET을 3D 구조로 제작하고, 이 기술을 적용하여 검증한다. 그리고 Silvaco simulation tool을 이용하여 S/D에 Metal이 Contact을 이루는 구조가 Double type과 Triple type에 따라 Contact Resistivity에 미치는 영향을 미리 확인하였고 이를 실험으로 검증하여 소자의 축소화에 따라 대두되는 문제점들의 해결책을 제시하고자 한다.