• Journal of the Korea Society of Computer and Information
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• v.9 no.1
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• pp.9-15
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• 2004

New WSW(Wrap Side Wall) is proposed to decrease junction electric field in this paper. WSW process is fabricated after first gate etch, followed NM1 ion implantation and deposition & etch nitride layer. New WSW structure has buffer layer to decrease electric field. Also we compared the hot carrier characteristics of WSW and conventional. Also, we design a test pattern including pulse generator, level shifter and frequency divider, so that we can evaluate AC hot carrier degradation on-chip. It came to light that the universality of the hot carrier degradation between DC and AC stress condition exists, which indicates that the device degradation comes from the same physical mechanism for both AC and DC stress. From this universality, AC lifetime under circuit operation condition can be estimated from DC hot carrier degradation characteristics.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.353-353
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• 2012

채널 도핑이 다른 비대칭 구조를 갖는 NMOSFET의 게이트 전압에 따른 Drain saturation current (IDSAT), maximum transconductance (GM) 및 threshold voltage (VT)와 같은 다양한 변수를 측정하였고 DAHC (Drain avalanche hot carriers) 스트레스에 따른 특성을 추출하였다. 전기적 특성은 반도체 파라미터 분석기를 사용하여 Probe system에서 진행되었다. 문턱전압은 Normal channel dopoing의 경우 0.67 V, High channel doping의 경우 0.74 V로 High channel doping된 소자가 상대적으로 높은 문턱전압을 보였다. Swing의 경우 Normal channel doping의 경우 87 mV/decade, high channel doping의 경우 92 mV/decade으로 High channel doping된 소자가 더 높은 Swing값을 보였다. 스트레스 인가 후 두 소자 모두 문턱전압이 증가하고 ON-current가 감소하였다. High channel doing된 소자의 경우 Normal channel doping된 소자보다 문턱전압의 증가율과 Current 감소율 측면 모두 스트레스에 더 민감하게 반응하였다. 문턱전압이 서로 다른 비대칭 NMOSFET의 핫 캐리어 특성을 비교, 분석결과 스트레스 인가에 따라 채널 도핑이 높아질수록 드레인과 게이트간의 더 높은 전계가 생겨 게이트 산화막과 Si/SiO2 계면의 손상이 더 발생하였다. 따라서 채널 도핑이 상대적으로 높은 트랜지스터가 핫 캐리어에 의한 계면 트랩 생성 비율이 더 높다는 것을 알 수 있다.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1994.06a
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• pp.404-408
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• 1994

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1995.06a
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• pp.678-681
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• 1995

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.10a
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• pp.656-659
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• 2001

Recently, as device techniques are advancing and its size become smaller, the hot carriers transport analysis has more important. Impact ionization(I.I.) effect is electron-hole pair generation process by the dispersion of hot carrier in the contrast with Auger process. Complete I.I. model is essential to simulate and analysis the device transport characteristics. In the study, we will try to analysis I.I. models using Monte Carlo simulator, TCAD and Micro-Tec and present more accurate I.I. model.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.8
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• pp.847-852
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• 2014

As the scaling trend becomes accelerated in process technology for cost reduction in semiconductor chip manufacturing, the requirement for shrink technology has increased. Hot Carrier Injection (HCI) degradation for I/O transistors is most concerning part when shrink. To solve this, the effective channel length (Leff) was increased using liner oxide before Light Doped Drain (LDD) implants and optimized the tilt angle to increase Leff without E-field degradation in LDD region, satisfying the HCI specification.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.9
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• pp.683-686
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• 1998

Hot carrier effects as a function of bias stress time and bias stress consitions were syste-matically investigated in p-channel poly-Si TFT s fabricated on the quartz substrate. The device degradation was observed for the negative bias stress, while improvement of electrical characteristic except for subthreshold slope was observed for the positive bias stress. It was found that these results were related to the hot-carrier injection into the gate oxide and interface states at the poly-Si/$SiO_2$interface rather than defects states generation within the poly-Si active layer under bias stress.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.365-368
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• 2002

WSW(Wrap Side Wall) is proposed to decrease junction electric field in this paper. WSW process is fabricated after first gate etch, followed NMI ion implantation and deposition & etch nitride layer New WSW structure has buffer layer to decrease electric field. Also we compared the hot carrier characteristics of WSW and conventional. Also, we design a test pattern including pulse generator, level shifter and frequency divider, so that we can evaluate AC hot carrier degradation on-chip.

• Information and Communications Magazine
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• v.32 no.7
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• pp.17-26
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• 2015

최근 네트워크 기술 동향에 있어서 이른바 핫 이슈 중 하나인 소프트웨어 정의 네트워킹(SDN, Software-Defined Networking)은 바야흐로 데이터센터, 기업, 캠퍼스 등의 근거리 데이터 네트워크(LAN, Local Area Network) 환경을 넘어서 통신망 사업자(캐리어)와 서비스 제공자를 통해 원거리 데이터 네트워크 (WAN, Wide Area Network)로 진화하고 있다. 본고에서는 종단간 SDN 프로덕션 서비스를 위한 소프트웨어 정의 원거리 네트워크(SD-WAN, Software-Defined WAN)의 개요 및 적용 사례를 소개하고, SD-WAN의 핵심 서비스 기술로 인식되고 있는 네트워크 최적화, 가상화, 자동화, SDX(Software-Defined Exchange) 등의 요소 기술과 연구 동향을 알아본다.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.11
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• pp.30-36
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• 1997

AlGaAs/GaAs HBTs are developed well enough to be commercialized as an active device in optical transmission system, but there remains the unanswered questions about reliability. In this paper we applied the reverse constant current stress at the high voltage in avalanche region for a long time to find out a new degradation mechanism of junctrion I-V. The unction off-set voltage at which the current vanishes to zero was shifted to the negative direction of applied bias due to the increment of leakage current as the stress time increases. It was identified that the degradation was induced by the hot carriers which were generated at space charge region and trapped at the interface between GaAs base and the passivation nitride enhancing the electric field across the nesa edge.