• Proceedings of the Korean Information Science Society Conference
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• 2000.04b
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• pp.214-216
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• 2000

본 논문에서는 유전자 프로그래밍을 이용하여 온라인 적응 학습이 가능 진화 하드웨어의 진화 전략을 구성하였다. 유전자 프로그래밍은 특유의 트리형 개체구조가 여러 개의 프로세스의 합을 통한 복합 임무의 수행 구조로 해석될 수 있다는 이점에 비하여, 하드웨어 구현이 어렵고 crossover 연산자의 사용이 어렵다는 단점등에 의하여 진화 하드웨어의 동적 재구성 알고리즘으로 널리 사용되지 못하였다. 본 논문에서는 유전자 프로그래밍의 이러한 단점을 극복할 수 있는 개체 표현 및 하드웨어 구현 방법을 제안하였으며, 제안된 방법론에 기존의 연구 결과를 결합하여 유전자 프로그래밍의 수행 효율을 높일 수 있는 진화 전략을 구성하였다. 제안된 진화 전략은 자율 이동 로봇 실험에 적용되어 효율성을 확인하였다.

• Journal of Internet of Things and Convergence
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• v.1 no.1
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• pp.33-38
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• 2015

Hardware are developed in various architecture. It is necessary to verifying value of variables in modules generated in each clock cycles for timing simulation. In this paper, a test vector generator in software type generates test vectors for timing simulation of 224-bit ECDSA hardware modules in developing stage. It provides test vectors with GUI format and text file format.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2004.10a
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• pp.134-137
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• 2004

지능 홈-케어 시스템 또는 외부 통신 채널의 환경 인식이 가능한 모바일 통신기기와 같은 상황 인식 시스템이 외부 상태를 감지하여 현재 상창을 인식하고 대처하기 위해서는 수 백개 이상의 규칙들을 이용한 추론을 필요로 한다. 이들 규칙들의 효과적인 추론을 위해서는 룰-베이스 시스템에 기반을 둔 추론 기법을 적용시킬 수 있다 이 룰-베이스 시스템의 추론 규칙의 매칭을 위해서 RETE 알고리즘이 사용되어 왔다. 하지만 RETE 알고리즘은 그 특성상 Von Neumann 구조의 컴퓨터 시스템에서는 규칙의 증가에 따른 그 성능의 저하가 필연적이다. 본 논문에서는 RETE 네트워크를 이용한 추론을 효과적으로 수행할 수 있는 RETE 네트워크 하드웨어 가속기의 구조에 대해서 논한다. 이 RETE 네트워크 하드웨어 가속기은 Von Neumann의 구조적 제약점을 병렬처리 구조를 사용하여 제거하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.7C
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• pp.540-547
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• 2008

In this paper, we proposed a new VLSI architecture which can generate computer-generated hologram (CGH) in real-time and implemented to hardware. The modified algorithm for high-performance CGH was introduced and re-analyzed (or designing hardware. from both numerical and visual analysis, the infernal number system of hardware was decided. CGH algorithm and precision analysis enabled to propose a new cell architecture for CGH. The operational sequence was analyzed with the architecture of CGH cell and the characteristics of the modified CGH algorithm, and finally the pipelined architecture and the operational timing were proposed.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.9 no.4
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• pp.414-418
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• 2016

In this paper, a hardware architecture of low area gradient magnitude calculator is proposed. For the hardware complexity reduction, the characteristic of orthogonal projection vector and hardware resource sharing technique are applied. The proposed hardware architecture can be implemented without degradation of the gradient magnitude data quality since the proposed hardware is implemented with original algorithm. The FPGA implementation result shows the 15% of logic elements and 38% embedded multiplier savings compared with previous work using Altera Cyclone VI (EP4CE115F29C7N) FPGA and Quartus II v15.0 environment.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.6
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• pp.22-34
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• 2010

Existing image scalers generally adopt simple interpolation methods such as bilinear method to take cost-benefit, or highly complex architectures to achieve high quality resulting images. However, demands for a low power, low cost, and high performance image scaler become more important because of emerging high quality mobile contents. In this paper we propose the novel low power hardware architecture for a high quality raster scan image scaler. The proposed scaler architecture enhances the existing cubic interpolation look-up table architecture by reducing and optimizing memory access and hardware components. The input data buffer of existing image scaler is replaced with line memories to reduce the number of memory access that is critical to power consumption. The cubic interpolation formula used in existing look-up table architecture is also rearranged to reduce the number of the multipliers and look-up table size. Finally we analyze the optimized parameter sets of look-up table, which is a trade-off between quality of result image and hardware size.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.1
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• pp.157-165
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• 2013

In this paper, efficient digit-serial VLSI architecture for 1D (9,7) lifting-based discrete wavelet transform (DWT) filter has been proposed. The proposed architecture computes the DWT in digit basis, so that the required hardware is reduced. Also, the multiplication is replaced with the shift and add operation to minimize the hardware requirement. Bit allocation for input, output, and the internal data has been determined by analyzing the PSNR. We have carefully designed the data feedback latency not to degrade the performance in the recursive folded scheduling. The proposed digit-serial architecture requires small amount of hardware but achieve 100% of hardware utilization, so we try to optimize the tradeoffs between the hardware cost and the performance. The proposed architecture has been designed and verified by VerilogHDL and synthesized by Synopsys Design Compiler with a DongbuHitek $0.18{\mu}m$ STD cell library. The maximum operating frequency is 330MHz with 3,770 gates in equivalent two input NAND gates.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.7B
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• pp.996-1005
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• 2001

본 논문에서는 ASIC 벤더의 셀 라이브러리와 MUX-based FPGA에 있는 고정된 입력을 갖는 연결구조의 수를 최소화하는 하드웨어 할당 알고리듬을 제안한다. 제안된 할당 알고리듬은 연산자간을 연결하는 신호선이 반복적으로 이용되어 연결 신호선 수가 최소가 될 수 있도록 연산자를 할당한다. 연결 구조를 고려한 이분할 그래프에 가중치를 설정하고 변수와 레지스터간의 최대 가중치 매칭을 구함으로써 레지스터 할당을 수행한다. 또한 연결구조에 대한 멀티플렉서의 중복 입력을 제거하고 연산자에 연결된 멀티플렉서간의 입력을 교환하는 입력 정렬 과정으로 연결구조를 최소화한다. 벤치마크 실험을 통하여 제안된 알고리즘의 효용성을 보인다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.2C
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• pp.150-159
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• 2002

This paper presents the convergence time, SER(Symbol Error Rate), MSE(Mean Square Error), hardware complexity and step-size(${\mu}$) about various LMS(Least Mean Square) algorithms in FS-DFE(Fractionally Spaced-Decision Feedback Equalize) for Cable Modem based on MCNS(Multimedia Cable Network System) DOCSIS(Data Over Cable Service Interface Specification) v1.0/v1.1 standards. We designed and simulated using ${SPW}^{TM}$ and synthesized using STD90 library through ${SYNOPSYS}^{TM}$. And also, we adopted the time-multiplexed multiplication and tap shared architecture in order to achieve the low hardware complexity. Simulation results show that DS-LMS algorithms[1][3] is the optimum solution about performace and hardware size. in high order QAM applications. Finally, we achieved area saving about 58% using DS-LMS algorithm compare with conventional equalizer architecture.

• Journal of the Korea Computer Graphics Society
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• v.23 no.3
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• pp.55-64
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• 2017

In this paper, a novel soft shadow method is suggested to support realistic shadows in mobile ray tracing. In ray tracing, soft shadow is generally generated by sampling a shadow ray. As this sampling method increases the number of rays to be processed, it has undermined the performance. We designed the proposed soft shadow processing method and hardware architecture to overcome this problem through selective shadow generation and triangle address caching for minimizing the performance degradation caused by sampling. The proposed hardware architecture can be integrated into a mobile ray-tracing hardware and was evaluated in terms of its performance on the FPGA. Based on the results, the rendering performance about 4, 8, and 16 samples were improved, respectively, by 40%, 50%, and 56% on average compared to the previous method, and it was found that the real-time soft shadow processing is feasible with the proposed hardware architecture.