• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.3
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• pp.108-115
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• 1990

This paper describes the design and fabrication of a processing element that will be used as a component in the construction of a two dimensional systolic for FFT. The chip performs data shuffling and radix-2 decimation-in-time (DIT) butterfly arithmetic. It consists of a data routing unit, internal control logic and HBA unit which computes butterfly arithmetic. The 6.5K transistors processing element designed with standard cells has been fabricated with a 2u'm double metal CMOS process, and evaluated by wafer probing measurements. The measured characteristics show that a HBA can be computed in 0.5 usec with a 20MHz clok, and it is estimated that the FFT of length 1024 can be transformed in 11.2 usec.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.9
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• pp.749-755
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• 2007

Recently, novel MEMS probe cards can support reliable wafer level chip test with high density probing capacity. However, manufacturing cost and process complexity are crucial weak points for low cost mass production. To overcome these limitations, we have developed micro spring structured MEMS probe card. For fabrication of micro spring module, a wire bonder and electrolytic polished gold wires are used. In this case, stringent tension force control is essential to guarantee the low level contact resistance of micro spring for reliable probing performance. For this, relation between tension force of fabricated probe card and contact resistance is characterized. Compare to conventional probe cards, developed MEMS probe card requires fewer fabrication steps and it can be manufactured with lower cost than other MEMS probe cards. Also, due to the small contact scratch patterns, we expect that it can be applied to bumping types chip test which require higher probing density.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.25 no.6
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• pp.285-289
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• 2015

With the miniaturization with both high functionality and high integrity of the probe cards, the highly precise laser punching on the zero-shrinkage high strength substrate has attracted more attention recently. Taper occurrence during laser-punching on green sheets appears as a problem in process. The size (diameter) difference between the entrance hole and the exit hole in tapered holes appeared to be inversely proportional to the hole size itself. To suppress taper occurrence, two-stage punching was adopted as the size of second hole was varied from $70{\mu}m$ to $79{\mu}m$ when punching $80{\mu}m$ via holes on the substrate with thickness of $380{\mu}m$. The minimal taper ratio of 11.9 % appeared with second hole size between 70 to $79{\mu}m$ before sintering. Taper ratio reduced to 7 % after zero-shrinkage sintering. The size difference between first hole and second hole appeared minimal when the size of second hole was 95~97 % to that of first hole.