• Journal of the Korean Institute of Telematics and Electronics
• /
• v.24 no.6
• /
• pp.1080-1086
• /
• 1987

SLAGEN, a system for symbolic cell layout based on artificial intelligence approach, takes as input a transistor connection description of CMOS standard cells and environment information, and outputs a symbolic layout description. SLAGEN performas transistor grouping by a heuristic search method, in order to minimize the number of separations, and then performs group reordering and transistor reordering with an eye toward minimizing routing. Next, SLAGEN creates a rough initial routing in order to guarantee functionality and correctness, and then improve the initial routing by a rule-based approach.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.23 no.6
• /
• pp.988-994
• /
• 1986

We present an automated CMOS standard cell design mehtodology which generates a mask description in the CIF (Caltech Intermediate Form)from a user-given logic description and design rule. The resultant layout reflects the user's choice among N-well, P-well and twin-well process and user's decision whether the guard band is to be included or not. Noise margin of each cell was improved by carefully adjusting the channel width of P-FET.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.37 no.2
• /
• pp.60-68
• /
• 2000

This paper describes a design methodology for the CMOS current source which can be implemented in standard memory process. The proposed techniques provide a good characteristic against the power-supply variation by utilizing a self-bias circuit and the reduction of the first-order component of the temperature variation through the new temperature compensation technique and include a new current-sensing start-up circuit enabling a robust operation against the voltage noise generated during the operation of the chip. In addition to the circuit-design technology, techniques where the proposed CMOS current-reference circuit can be applied to the clocking circuits of a very high-speed DRAM are presented. The feasibility of the suggested design methodology for the CMOS current reference is demonstrated by both the analytical method and the circuit simulation.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.18 no.3
• /
• pp.397-409
• /
• 1993

This paper proposed the design methodology of the 8 bit binary parallel adder with carry book-ahead scheme via current-mode CMOS multivalued logic and simulated the proposed adder under $5{\mu}m$ standard IC process technology. The threshold conditions of $G_K$ and $P_K$ which are needed for m-valued parallel adder with CLA are evaluated and adopted for quaternary logic. The design of quaternary CMOS logic circuits, encoder, decoder, mod-4 adder, $G_K$ and $P_K$ detecting circuit and current-voltage converter is proposed and is simulated to prove the operations. These circuits are necessary for binary arithmetic using multivalued logic. By comparing with the conventional binary adder and the CCD-MVL adder, We show that the proposed adder cab be designed one look-ahead carry generator with 1-level structure under standard CMOS technology and confirm the usefulness of the proposed adder.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.6
• /
• pp.28-36
• /
• 2008

This paper describes a low-power CMOS analog front-end block for UHF band RFID tag chips. It satisfies ISO/IEC 18000-6C and includes a memory block for test. For reducing power consumption, it operates with an internally generated power supply of 1V. An ASK demodulator using a current-mode schmitt trigger is proposed and designed. The proposed demodulator can more exactly demodulate than conventional demodulator with low current consumption. It is designed using a $0.18{\mu}m$ CMOS technology. Measurement results show that it can operate properly with an input as low as $0.25V_{peak}$ and consumes $2.63{\mu}A$. The chip size is $0.12mm^2$.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.8 no.7
• /
• pp.1424-1428
• /
• 2004

In this paper, CMOS analog filters for use in the Analog front End of digital subscriber loop(DSL) chip set are proposed. Designed filters contain receiver continuous-time filters which are composed of lowpass and highpass functions. And their cutoff frequency are 138H1z and 1.1MHz respectively. A low-voltage gm-c integrator is improved and used to design filters. Desisned filters are verified by HSPICE simulation with the 0.25${\mu}m$ CMOS n-well parameter.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.46 no.1
• /
• pp.94-101
• /
• 2009

This paper presents scalable modeling of spiral inductors for RFIC design based on $0.13{\mu}m$ RF CMOS process. For scalable modeling, several inductor patterns are designed and fabricated with variations of width, number of turns and inner radius. Feeding structures are optimized for accurate de-embedding of pad effects. After measuring the S parameters of the fabricated patterns, double-$\pi$ equivalent circuit parameters are extracted for each device and their geometrical dependences are modeled as scalable functions. The inductor library provides two types of models including standard and symmetric inductors. Standard and symmetric inductors have the range of $0.12{\sim}10.7nH$ and $0.08{\sim}13.6nH$ respectively. The models are valid up to 30GHz or self-resonance frequency. Through this research, a scalable inductor library with an error rate below 10% is developed for $0.13{\mu}m$ RF CMOS process.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.12
• /
• pp.80-86
• /
• 2009

In this paper, we present a new charge pump circuit feasible for the implementation with standard twin-well CMOS process technology. The proposed charge pump employs PMOS-switching dual charge-transfer paths and a simple two-phase clock. Since charge transfer switches are fully turned on during each half of clock cycle, they transfer charges completely from the present stage to the next stage without suffering threshold voltage drop. During one clock cycle, the pump transfers charges twice through two pumping paths which are operating alternately. The performance comparison by simulations and measurements demonstrates that the proposed charge pump exhibits the higher output voltage, the larger output current and a better power efficiency over the traditional twin-well charge pumps.

• Proceedings of the IEEK Conference
• /
• 1999.11a
• /
• pp.851-854
• /
• 1999

A high efficient, CMOS RF power amplifier at a 2.SV power supply for the band of 902-928MHz was designed and analyzed in 0.25${\mu}{\textrm}{m}$ standard CMOS technology. The output power of designed amplifier is being digitally controlled from a minimum of 2㎽ to a maximum of 21㎽, corresponding to a dynamic range of l0㏈ power control. The frequency response of this power amplifier is centered roughly at 915MHz. The power added efficiency of designed amplifer is almost 48% at maximum output power of 21㎽.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.19 no.11
• /
• pp.994-999
• /
• 2006

For low-cost embedded EEPROM, in this paper, single polysilicon EEPROM and n-channel high-voltage LDMOST device are developed in a $0.25{\mu}m$ standard CMOS logic process. Using these devices developed, the EEPROM chip is fabricated. The fabricated EEPROM chip is composed of 1 Kbit single polysilicon EEPROM away and high voltage driver circuits. The program and erase characteristics of the fabricated EEPROM chip are evaluated using 'STA-EL421C'. The fabricated n-channel high-voltage LDMOST device operation voltage is over 10 V and threshold voltage window between program and erase states of the memory cell is about 2.0 V.