• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.05a
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• pp.206-209
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• 2002

본 논문에서는 폴리실리콘의 재결정화 공정에서 발생하기 쉬운 폴리실리콘의 엉김현상, 슬립, 부분적인 실리콘 기판의 녹음현상 등을 방지하기 위한 방법을 제시한다. 그리고 재결정화 된 박막의 질을 향상시키기 위한 폴리실리콘과 보호 산화막(capping oxide)의 두께 변화에 따른 실험 결과를 살펴본다. 폴리실리콘의 엉김현상은 매몰 산화막(buried oxide)과 액체 상태의 실리콘 사이의 wetting angle과 관계되는데, 이를-방지하기 위해서는 재결정화할 폴리실리콘과 산화막의 계면에 질소를 주입시켜주면 되는데, 이는 재결정화할 시료를 암모니아 가스 분위기에서 열처리를 통하여 해결할 수 있다. 그러고 실러콘 기판의 국부적 녹음 현상 및 슬립은 실리콘 기판의 윗면을 mechanical damage에 의해서 약 $20{\mu}m$ 정도의 거칠기를 가지도록 하면 이러한 현상을 방지할 수 있다. 그러고 폴리실리콘이 재결정활 될 때 부피의 변화가 발생하며, 이로 인하여 재결정화된 박막의 두께는 위치에 따라 변화한다. 재결정화된 박막 두께의 균일도를 유지하기 위해서는 재결정화할 폴리실리콘 두께의 3배 이상이 되는 보호 산화막을 사용하였을 때 원하는 균일도를 얻을 수 있었다.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.244.2-244.2
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• 2016

폴리 실리콘 박막은 저온 안정성, 산화 안정성, 가스 투과성 및 전기재료로서의 우수한 물성 때문에 산업에서 계속적으로 넓게 쓰이고 있다. 특히 최근 높은 색 재현율과 고화질로 각광을 받고 있는 능동형 유기발광 다이오드 (AMOLED)를 위한 Thin Film Transistor (TFT)는 신뢰성 및 우수한 특성이 요구되기 때문에 반드시 폴리실리콘 TFT가 적용되어야 한다. 이러한 이유 때문에 아모포스 실리콘을 폴리실리콘으로 결정화 시키는 방법들이 많이 연구 되어져왔다. 이 연구에서는 아모포스 실리콘 박막을 고품질의 폴리실리콘 박막으로 제조하기 위해, 기판에 positive DC 전압을 펄스 형태로 인가함으로써, 기판에 입사되는 전자를 이용한 열처리 방법을 사용하였다. 열처리 온도는 기판에 들어오는 current값을 조절함으로써 제어할 수 있었다. 열처리를 위해 사용 된 수소화 된 아모포스 실리콘은 Low Pressure Chemical Vapor Deposition (LPCVD)장비로 530도에서 증착 되었으며, 이러한 아모포스 실리콘 박막은 공정시간 60 s 이내에 샘플 표면온도가 600도 이상으로 증가함으로써 균일한 폴리실리콘 막으로 제조 되었다.

• Korean Journal of Materials Research
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• v.2 no.3
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• pp.180-190
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• 1992

Some solutions to several major problems in ZMR such as agglomeration of polysilicon, slips and local substrate melting are described. Experiments are performed with varying polysilicon thickness and capping oxide thickness. The aggmeration can be eliminated when nitrogen is introduced at the capping oxide layer-to-polysilicon interface and polysilicon-to-buried oxide layer interface by annealing the SOI samples at $1100^{\circ}$ in $NH_3$ ambient for three hours. The slips and local substrate melting are removed when the back surface of silicon substrate is sandblasted to produce the back surface roughness of about $20{\mu}m$. The subboundary spacing increases with increasing polysilicon thickness and the uniformity of recrystallized SOI film thickness improves with increasing capping oxide thickness, improving the quality of recrystallized SOI film. When the polysilicon thickness is about $1.0{\mu}m$ and the capping oxide thickness is $2.5{\mu}m$, the thickness variation of the recrystallized SOI film is about ${\pm}200{\AA}$ and the subboundary spacing is about $70-120{\mu}m$.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.6 no.3
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• pp.261-264
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• 2005

The 90 nm gate pattern technology have been virtualized by employing the hard mask and the planarization of fate poly silicon. We fabricated 70nm poly-Si on $200 nm-SiO_2/p-Si(100)$ substrates using low pressure chemical vapor deposition (LPCVD) to investigate roughness evolution by varying rapid annealing temperatures. The samples were annealed at the temperatures of $700^{\circ}C\~1100^{\circ}C$ for 40 seconds with a rapid thermal annealer. The surface image and the surface roughness were measured by a field emission scanning electron microscopy (FESEM) and an atomic force microscopy (AFM), respectively. The poly silicon surface became more rough as temperature increased due to surface agglomeration. The optimum conditions of poly silicon planarization were achieved by annealed at $700^{\circ}C$ for 40 seconds.

• Journal of the Korean Vacuum Society
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• v.4 no.S1
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• pp.13-20
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• 1995

As으로 in-situ 도핑된 폴리실리콘 막을 원하는 부위에만 선택적으로 증착시킬 수 있는 RTP-CVD 증착기술이 성공적으로 수행되었다. 막의 증착속도는 도핑량이 증차함에 따라 점차 감소하였으나 As의 양이 5ppm보다 커지자 급격히 감소하였다. 또한 증착속도는 As의 유량이 일정할 때, SiH2CI2 유량에 따라 직선적으로 변화하였다. As 도펀트의 농도는 막내부에 비해 폴리실리콘/실리콘기판의 계면과 표면에서 상대적으로 높게 나타났으며, 특히 증착온도가 낮을 때 As 도펀트의 농도는 더 높아짐을 알 수 있었다. 실리콘 표면에서 약 40-50nm 위치에서 도펀트의 농도천이가 급격히 일어났으며, 그 결과 RTP-CVD공정을 이용할 때 극히 얕고 일정한 깊이분포를 갖는 n+-p junctions were achieved and laterally uniform delineated junctions were also observed using RTP-CVD.

• Korean Chemical Engineering Research
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• v.46 no.1
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• pp.37-49
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• 2008

Recent rapid progress in the photovoltaic industry has seriously been retarded by limited supply of polysilicon used as the feedstock for silicon wafer-based solar cells. It is thus believed that development of a competitive process for preparing polysilicon with the quality required for solar cells can greatly enhance the competitiveness and extent of the photovoltaic application. Technologies currently available for preparing the silicon feedstock are reviewed with the recent fluidized bed silicon deposition process being discussed in more details in terms of key technical barriers.

• Korean Journal of Materials Research
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• v.3 no.2
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• pp.158-165
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• 1993

Abstract To investigate the effect of underlying Si on the thermal stability of the TiS$i_2$ film, TiS$i_2$ films obtained by the solid-state reaction of the Ti film on as-deposited or on heat-treated poly-silicon and amorphous-silicon were annealed at 90$0^{\circ}C$ for various times. The poly-Si film was evaluated by XRD, SEM and TEM. The thermal stability of the TiS$i_2$ film was evaluated by measuring the sheet resistance and microstructural evolution during furnace annealing. Agglomeration of the TiSi, film occurred more on amorphous-Si than on poly-Si. The thermal stability of the TiS$i_2$ film was improved by annealing poly-Si. The Si layer crystallized from amorphous-Si has an equiaxed structure with the (111) preferred orientation whereas for as-deposited poly-Si has a columnar structure with the (110) orientation. Better thermal stability of the TiS$i_2$ film can be obtained by the higher surface energy of underlying poly-Si.

• Journal of Sensor Science and Technology
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• v.8 no.1
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• pp.53-62
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• 1999

Micro polysilicon actuators, which are widely used in the field of MEMS (Microelectromechanical System) technology, were fabricated using polysilicon thin layers. Polysilicon deposition were carried out to have symmetrical layer structures with a LPCVD (Low Pressure Chemical Vapor Deposition) system, and we have measured physical characteristics by micro test patterns, such as bridges and cantilevers to verify minimal mechanical stress and stress gradient in the polysilicon layers according to the methods of mutilayer deposition, doping, and thermal treatment, also, analyzed the properties of each specimen, which have a different process condition, by XRD, and SIMS etc.. Finally, the fabricated planar polysilicon resonator, symmetrically stacked to $6.5{\mu}m$ thickness, showed Q of 1270 and oscillation ampitude of $5{\mu}m$ under DC 15V, AC 0.05V, and 1000 mtorr pressure. The developed micro polysilicon resonator can be utilized to micro gyroscope and accelerometer sensor.

• Journal of the Korean Institute of Gas
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• v.22 no.4
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• pp.55-62
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• 2018

There is growing interest in solar power generation due to global warming. As a result, demand for polysilicon, which is the core material for solar cells, is increasing day by day. As the market grows, large and small accidents occurred in the production process. In 2013, hydrochloric acid leaked from the polysilicon manufacturing plant in SangJu. In 2014, a fire occurred at a polysilicon manufacturing plant in Yeosu, and in 2015, STC(Silicon Tetrachloride) leaked at a polysilicon manufacturing plant in Gunsan City. Leakage of chemicals in the polysilicon manufacturing process can affect not only the workplace but also the surrounding area. Therefore, in this study, we identified the hazardous materials used in the polysilicon manufacturing process and quantitatively estimate the amount of leakage and extent of damage when the worst case scenario is applied. As a result, the damage distance by explosion was estimated to be 726 m, and the damage distance to toxicity was estimated to be 4,500 m. And, if TCS(Trichlorosilane), STC(Silicon Tetrachloride), DCS(Dichlorosilane) leaks into the air and reacts with water to generate HCl, the damage distance is predicted to 5.7 km.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.136-136
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• 2010

본 연구에서는 귀금속 촉매 식각법을 이용하여 고효율의 태양전지 응용을 위한 p형 실리콘 와이어 어레이를 제조 하였다. 실리콘 와이어 어레이를 기판에서 분리하기 위해 고무 상의 고분자인 폴리디메틸실록산 (polydimethylsiloxane)을 스핀 코팅을 이용하여 실리콘 와이어 어레이 위에 증착하였다. 희석제의 함량과 스핀코팅의 회전수에 따라 폴리디메틸실록산의 박막두께를 조절하였으며, 기계적 방법으로 실리콘 와이어 어레이를 기판에서 분리할 수 있음을 보여주었다.