• Proceedings of the KAIS Fall Conference
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• 2012.05b
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• pp.690-692
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• 2012

전도도가 우수한 알루미늄 및 알루미나 소재를 사용하여 LED 패키지를 제작하였다. 선택적 양극산화 공정을 적용하여 알루미늄 기판 상에 알루미나를 형성하고 이를 유전체로 사용하였다. 패키지 기판에 따른 열저항 및 광량 분석을 위해 알루미늄 기판과 알루미나 기판을 제작하여 성능 비교분석을 진행하였다. 알루미늄 기판이 알루미나 기판보다 우수한 열저항 및 발광효율 특성을 보여주었으며, 이러한 결과는 선택적 양극산화 공정을 사용한 알루미늄 기판이 고출력 LED 패키지용 기판으로 활용할 수 있음을 보여준다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.69-74
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• 2010

A new package substrate for dynamic random access memory(DRAM) devices has been developed using selective aluminum anodization. Unlike the conventional substrate structure commonly made by laminating epoxy-based core and copper clad, this substrate consists of bottom aluminum, middle anodic aluminum oxide and top copper. Anodization process on the aluminum substrate provides thick aluminum oxide used as a dielectric layer in the package substrate. Placing copper traces on the anodic aluminum oxide layer, the resulting two-layer metal structure is completed in the package substrate. Selective anodization process makes it possible to construct a fully filled via structure. Also, putting vias directly in the bonding pads and the ball pads in the substrate design, via in pad structure is applied in this work. These arrangement of via in pad and two-layer metal structure make routing easier and thus provide more design flexibility. In a substrate design, all signal lines are routed based on the transmission line scheme of finite-width coplanar waveguide or microstrip with a characteristic impedance of about $50{\Omega}$ for better signal transmission. The property and performance of anodic alumina based package substrate such as layer structure, design method, fabrication process and measurement characteristics are investigated in detail.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.11a
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• pp.67-67
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• 2002

패키지 기술의 개발은 저비용, 고성능, 높은 패키징 효율의 추세로 가고 있다. 이러한 추세에 따라 기판재료의 개발 및 구조의 변형이 요구된다. 패키지의 한 형태인 MCM(Multi-Chip Module)에 연성기판을 사용할 경우 fine pattern이 가능하고 부피가 작기 때문에 패키지의 효율이 좋고 또한 reel to reel process에 적용이 가능하기 때문에 대량생산의 이점을 가지고 있다. 연성기판은 좋은 전기적 특성을 가진 polyimide와 구리 층으로 구성된다. 그러나 polyimide와 구리 계층 사이에 약한 접착력과 구리로의 polyamic acid의 diffusion, 다층 기판의 제조의 어려움 등의 문제점을 남겨두고 있다. 본 연구는 일반적인 polyimide/copper가 구조가 가지고 있는 문제점을 해결하고 구리 패턴을 제작하기 위해 에칭을 쓰는 것을 배제함으로 fine pattern을 이루어 내었으며 전기도금으로 완전하게 채워진 pluged via을 사용함으로 각층간의 연결에 신뢰성을 부여하였다. 또한, 연성기판의 구조적인 문제점인 해결하여 다층 연성기판을 제조하려고 한다.

• Electronics and Telecommunications Trends
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• v.10 no.1 s.35
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• pp.47-57
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• 1995

최근 전자 및 통신기기에는 시스템의 소형화, 고기능 및 고신뢰도를 실현하기 위하여 하나의 기판위에 여러개의 chip을 장착하는 다중칩 패키지 기술이 사용되고 있다. 그러나 이로 인하여 기판 면적당 칩수의 증가로 power dissipation이 증가하게 되었으며, 이러한 power의 증가는 온도를 상승시켜서 시스템의 신뢰도를 저하시키는 원인이 되고 있기 때문에 이에 대한 열 해석이 요구되어진다. 따라서 본 고에서는 다중칩 패키지의 열 성능을 위하여 전도성이 좋은 세라믹 기판의 과도 온도 특성을 해석하고자, 전기적 유사 회로를 이용하여 thermal via가 없는 경우와 있는 경우에 대하여 열전달 특성을 고찰하였다. 그 결과 themal via에 의한 기판의 열전달 향상으로 다중칩 패키지의 동작 온도가 낮아짐을 알 수 있었다.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.3
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• pp.853-858
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• 2010

DRAM package substrate has been demonstrated using a thick alumina layer produced by aluminum anodization process. To apply a transmission-based design methodology, 2 dimensional electromagnetic simulation is performed. The design parameters including signal line width/spacing and alumina's thickness are optimized based on the simulation analysis and are verified with the fabrication and the measurement of the test patterns on the anodic alumina substrate. DDR2 DRAM package is chosen as a design vehicle. Aluminum anodization technique has been applied successfully to fabricate new DRAM package substrate.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.39 no.1
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• pp.49-57
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• 2002

Including RF Package inductance, substrate coupling through conductive silicon(Si)-substrate is modeled and quantitatively characterized. 2-port substrate coupling model is extended for the characterization of multi-port substrate coupling between digital circuit block and analog/RF circuit block. Furthermore, scalable parameter extraction model is developed. Multi-port substrate coupling can be investigated by linearly superposing a frequency-dependent 2-port substrate coupling model using scalable parameters. In addition, Substrate coupling including RF package inductance effect is quantitatively investigated. It is shown that package effect increases substrate coupling and shifts a characteristic frequencies(i.e., poles) to the higher frequency range. The proposed methodology can be efficiently used to the mixed-signal circuit performance verification.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.10
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• pp.4757-4761
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• 2012

LED chip on board(COB) package has been fabricated using aluminum substrate and aluminum anodization process. An alumina layer, used as a dielectric in COB substrate, is produced on aluminum substrate by selective anodization process. Also, selective anodization process makes it possible to construct a thermal via with a fully-filled via hole. Two types of the COB package are fabricated in order to analyze the effects of their substrate types on thermal resistivity and luminous efficiency. The aluminum substrate with the thermal via shows more improved measurement results compared with the alumina substrate. These results demonstrate that selective anodization process and thermal via can increase heat dissipation of COB package in this work. In addition, it is proved experimentally that these parameters also can be enhanced using efficient layout of multiple chip in the COB package.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.7
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• pp.76-81
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• 2011

A new via cutting structure in 2-layer DRAM package substrate has been fabricated to lower its power distribution network(PDN) impedance. In new structure, part of the via is cut off vertically and its remaining part is designed to connect directly with the bonding pad on the package substrate. These via structure and substrate design not only provide high routing density but also improve the PDN impedance by shortening effectively the path from bonding pad to VSSQ plane. An additional process is not necessary to fabricate the via cutting structure because its structure is completed at the same time during a process of window area formation. Also, burr occurrence is minimized by filling the via-hole inside with a solder resist. 3-dimensional electromagnetic field simulation and S-parameter measurement are carried out in order to validate the effects of via cutting structure and VDDQ/VSSQ placement on the PDN impedance. New DRAM package substrate has a superior PDN impedance with a wide frequency range. This result shows that via cutting structure and power/ground placement are effective in reducing the PDN impedance.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.2
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• pp.61-68
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• 2015

Warpage analysis has been performed for top and bottom packages of thin package-on-packages processed with different epoxy molding compounds (EMCs). Warpage deviation was measured for packages molded with the same EMCs and also the warpage deviations of top and bottom substrates themselves were characterized in order to identify the major factor causing the package warpage. For the top and bottom packages processed with thin substrates, the warpage deviation of the substrates was large, which made it difficult to figure out the effect of EMC properties on the package warpage. Top packages, where the molding area of $13mm{\times}13mm$ covered the most of the substrate area ($14mm{\times}14mm$), exhibited similar warpage behavior with changing the temperature. On the other hand, bottom packages, where the molding area was only $8mm{\times}8mm$, exhibited the complex warpage behavior due to simultaneous occurrence of (+) and (-) warpages on the same package. Accordingly, the bottom packages showed dissimilar temperature-warpage behavior even being processed with the same EMCs.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.3
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• pp.63-69
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• 2013

The warpage of a bottom package of Package on Package(PoP) where a chip was mounted to a substrate by flip chip process was compared to that of a bottom package for which a chip was bonded to a substrate using die attach film(DAF). At the solder reflow temperature of $260^{\circ}C$, the packages processed with flip chip bonding and DAF bonding exhibited warpages of $57{\mu}m$ and $-102{\mu}m$, respectively. At the temperature range between room temperature and $260^{\circ}C$, the packages processed with flip chip bonding and DAF bonding exhibited warpage values ranging from $-27{\mu}m$ to $60{\mu}m$ and from $-50{\mu}m$ to $-15{\mu}m$, respectively.