• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.3A
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• pp.151-156
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• 2012

In this paper, design of quasi-cyclic(QC) low-density parity-check codes is proposed to have full diversity for space-time bit-interleaved coded modulation(ST-BICM) systems. Necessary and sufficient conditions that the proposed scheme has full diversity are proved as the condition that submatrices corresponding to the system part of codewords are invertible. And new construction method of binary invertible matrices for QC LDPC codes in ST-BICM systems are also proposed and modification for parity-check matrices are also explained.

• Proceedings of the Korea Multimedia Society Conference
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• 2003.05b
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• pp.229-233
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• 2003

오늘날 많은 양의 데이터가 디지털 논리 회로와 상호 연결에 의해서 다양한 컴퓨터 시스템과 서브시스템 사이에서 전송된다. 데이터가 전송될 때 전자적 잡음, 장치 결함, 시간 오류 등에 의해서 오류가 발생한다. 일반적으로 비트 오류가 발생했을 때 패리티 검사회로가 사용된다. 시스템의 신뢰성과 유용성을 높이기 위해서는 효율적인 패리티 검사회로가 요구된다. 본 논문에서는 PBCA의 특성행렬을 이용하여 거리가 3인 부호를 생성하는 방법과 오류 정정에 사용되는 행렬을 구성하는 방법 및 복호기법을 제시한다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39C no.7
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• pp.515-520
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• 2014

In this paper, the protograph-based block low density parity check (LDPC) code, which improves the performance and reduces the encoder/decoder complexity than the conventional Digital Video Broadcasting Satellite Second Generation (DVB-S2) LDPC code used for the marine satellite communication, is proposed. The computer simulation results verify that the proposed protograph-based LDPC code has the better performance in both the bit error rate (BER) and the frame error rate (FER) than the conventional DVB-S2 LDPC code. Furthermore, by analyzing the encoding and decoding computational complexity, we show that the protograph-based block LDPC code has the efficient encoder/decoder structure.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.2C
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• pp.219-228
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• 2010

In this paper, performance of RS (Reed-Solomon), turbo and LDPC (low density parity check) code in the binary symmetric erasure channel is investigated. When the average erasure length is reduced, the frequency of short erasures is increased. The RS code shows serious performance degradation in such an environment since decoding is carried out symbol-by-symbol. As the erasure length is increased, however, the RS code shows much improved en-or performance. On the other hand, the message and corresponding parity symbols of the turbo code can be erased at the same time for the long erasures. Accordingly, iterative decoding of the turbo code can not improve error performance any more for such a long erasure. The LDPC code shows little difference in error performance with respect to the variation of the average erasure length due to the virtual interleaving effect. As a result, the LDPC code has much better erasure decoding performance than the RS and turbo code.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.9
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• pp.1728-1730
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• 2015

In this letter, a parity check based iterative IC scheme is proposed for LDPC coded MIMO systems. After the decoding procedures in each iteration of the proposed scheme, each decoded codeword is utilized for the IC procedures only when the ratio of the check nodes satisfying the parity check equations to the total number of check nodes is not smaller than the pre-defined threshold value. Simulation results verify that the proposed scheme can achieve an improved BLER at the high SNR region compared to the conventional iterative IC scheme.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.5
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• pp.1149-1159
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• 1998

This paper presents the Controllable Self-Checking(CSC) Checker at which can be used the Fault-Tolerant System with the redundancy. According to the critical level of output(of system), especially, it can be instructed the time if it has to check the output or not. We adop the deterministic test, performed on-line, to detect the faults with a minimal test set. The results show the Parity 2-rail checker(P-TRC) which is designed much simpler than the checker has the higher fault coverage than the existent checker.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.9
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• pp.803-815
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• 2000

최근 처리해야 하는 정보의 양의 급속히 배가됨에 따라 디스크 배열(disk array) 시스템에서 사용하는 디스크의 수가 증가되는 경향을 보이고 있다. 그러나 많은 수의 디스크를 이용하여 디스크 배열을 구성하게 되면 디스크 오류 발생 확률을 높이는 결과로 이어지게 된다. 이 논문에서는 많은 수의 디스크를 사용하는 환경에서도 높은 신뢰성을 제공하기 위하여 DH(Diagornal-Horizontal) 기법이라 불리는 두가지 형태의 이중 패리티 배치 기법들을 제안한다 제안한 기법들은 사선 패리티와 수평 패리티를 인코딩하여 이용함으로써 디스크 배열에서 이중 디스크 오류의 복구가 가능하다. DH 기법들의 특징은 알고리즘이 단순하고, N을 임의의 소수라고 할 때 N 또는 N+1개의 디스크를 기반으로 쉽게 구현할 수 있다. 기본적으로 제안하는 기법들은 검사정보 저장을 위해 최적의 디스크 공간을 사용하고, 인코딩이나 디코딩 과정에서 단지 XOR 연산만을 필요로 하기 때문에 하드웨어의 수정 없이 기존의 디스크 배열 시스템에 쉽게 응용할 수 있다. 더욱이 치명적 오류를 방지할 수 있는 두 오류 디스크에 대한 복구 시간은 디코딩에서의 XOR 연산수를 최소화함으로써 신속하게 처리할 수 있다. 결과적으로 제안하는 기법들은 디스크 배열 시스템에서의 치명적 오류 확률을 낮출 수 있는 효과적인 방법이다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.12C
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• pp.991-996
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• 2008

In this paper, we propose an LDPC-coded hybrid ARQ system using incremental redundancy and retransmission of a part of the transmitted packets. We also present a simple criterion for choosing two methods to support a desired throughput efficiently. Furthermore, we show that the throughput performance can be improved when multi-edge type LDPC codes with the structure of Raptor codes are employed for a hybrid ARQ scheme.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.5C
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• pp.423-431
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• 2010

In this paper, a modified sum-product algorithm to correct bit errors captured within the trapping sets, which are produced in decoding of low-density parity-check (LDPC) codes, is proposed. Unlike the original sum-product algorithm, the proposed decoding method consists of two stages. Whether the main cause of decoding failure is the trapping sets or not is determined at the first stage. And the bit errors within the trapping sets are corrected at the second stage. In the modified algorithm, the set of failed check nodes and the transition patterns of hard-decision bits are exploited to search variable nodes in the trapping sets. After inverting information of the variable nodes, the sum-product algorithm is carried out to correct the bit errors. As a result of simulation, the proposed algorithm shows continuously improved error performance with increase in the signal-to-noise ratio. It is, therefore, considered that the modified sum-product algorithm significantly reduces or possibly eliminates the error floor in LDPC codes.

• Proceedings of the Korea Information Processing Society Conference
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• 2010.04a
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• pp.631-634
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• 2010

기존의 Quasi-Cyclic LDPC 부호는 하나의 기본행렬의 순환행렬을 부행렬로 사용하여 패리티 검사 행렬을 만든다. 본 논문에서는 무게가 서로 다른 두 개의 기본 행렬의 순환행렬들과 영행렬을 부행렬로 사용하고, 이 세 개의 부행렬들을 주어진 조건하에서 무작위로 조합하여 패리티 검사 행렬을 만드는 방법을 제안한다. 제안된 LDPC 부호는 girth가 6이상인 Irregular LDPC 부호이다.