• Korea Petroleum Association Journal
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• no.8 s.90
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• pp.108-111
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• 1988

• Korea Petroleum Association Journal
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• no.4 s.86
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• pp.114-116
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• 1988

• Environmental engineer
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• v.21 s.218
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• pp.60-65
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• 2004

• Journal of the Korean Society for Marine Environment & Energy
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• v.19 no.1
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• pp.52-61
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• 2016

To inject huge amount of $CO_2$ for CCS application, high pressure pipeline transport is accompanied. Rapid depressurization of $CO_2$ pipeline is required in case of transient processes such as accident and maintenance. In this study, numerical analysis on the depressurization of high pressure $CO_2$ pipeline was carried out. The prediction capability of the numerical model was evaluated by comparing the benchmark experiments. The numerical models well predicted the liquid-vapor two-phase depressurization. On the other hands, there were some limitations in predicting the temperature behavior during the supercritical, liquid phase and gaseous phase expansions.

• The Journal of the Korea Contents Association
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• v.10 no.8
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• pp.159-167
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• 2010

Since success of in the box office, there are not only highly interested in 3D Stereoscopic in Media market but also has been briskly supporting for 3D Stereoscopic producing in variety platforms including film, broadcasting, mobile They expect 3D Stereoscopic will be a new standard format for media of domestic market as well as overseas. However there are required professional production system and grant capital for 3D Stereoscopic production. In case of domestic industry, there are not forged through specialized production system and lack of 3D Stereoscopic producing. They are needed not only Pipeline for 3D Stereoscopic production but also strategic supporting like specialized education and test-bed for 3D Stereoscopic production. It is able to established efficient and specialized system for 3D Stereoscopic production given the pipeline proposal.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.12
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• pp.2333-2340
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• 2016

A LEA (Lightweight Encryption Algorithm) crypto-processor was designed, which supports three master key lengths of 128/ 192/256-bit, ECB and CTR modes of operation. To achieve high throughput rate, the round transformation block was designed with 128 bits datapath and a pipelined structure of 16 stages. Encryption/decryption is carried out through 12/14/16 pipelined stages according to the master key length, and each pipelined stage performs round transformation twice. The key scheduler block was optimized to share hardware resources that are required for encryption, decryption, and three master key lengths. The round keys generated by key scheduler are stored in 32 round key registers, and are repeatedly used in round transformation until master key is updated. The pipelined LEA processor was verified by FPGA implementation, and the estimated performance is about 8.3 Gbps at the maximum clock frequency of 130 MHz.

• KSCE Journal of Civil and Environmental Engineering Research
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• v.10 no.1
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• pp.57-69
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• 1990

The static nonlinear analysis of offshore pipeline is carried out by the finite element method. The governing equilibrium equation are derived by the principle of minimum potential energy and the modified Newton-Raphson procedure is used to solve the system of nonlinear algebraic equation. Geometrically nonlinear beam elements and spring elements are utilized to model the pipeline, stinger, pipe supports and seabed simultaneously. The beam element developed can be used to model redundant structures. It provides for both the torsional deformation and elongation of pipeline, and permits the use of different physical properties in each principal direction. The validity of this method is investigated by comparing the results with these obtained by other methods.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.4
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• pp.85-94
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• 2003

The asynchronous design methods proved to have the higher performance in power consumption and execution speed than synchronous ones because it just needs to activate the required module without feeding clock in the system. Despite the advantage of CISC machine providing the variable addressing modes and instructions, its execution scheme is hardly suited for a synchronous Pipeline architecture and incurs a lot of overhead. This paper proposes a novel asynchronous pipeline architecture, A80sl, whose instruction set is fully compatible with that of Intel 80C51, an embedded micro controller. We classify the instructions into the group keeping the same execution scheme for the asynchronous pipeline and optimize it eliminating the bubble stage that comes from the overhead of the multi-cycle execution. The new methodologies for branch and various instruction lengths are suggested to minimize the number of states required for instructions execution and to increase its parallelism. The proposed A80C51 architecture is synthesized with 0.35${\mu}{\textrm}{m}$ CMOS standard cell library. The simulation results show higher speed than that of Intel 80C51 with 36 MHz and other asynchronous counterparts by 24 times.

• The Transactions of the Korea Information Processing Society
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• v.5 no.5
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• pp.1172-1184
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• 1998

ILP(Instruction Level Parallelism) processors use code reordering algorithms to expose parallelism in a given sequential program. When applied to a loop, this algorithm produces a software-pipelined loop. In a software-pipelined loop, each iteration contains a sequence of parallel instructions that are composed of data-independent instructions collected across from several iterations. For vector loops, however the software pipelining technique can not expose the maximum parallelism because it schedules the program based only on data-dependencies. This paper proposes to schedule differently for vector loops. We develop an algorithm to detect vector loops at object code level and suggest a new vector scheduling algorithm for them. Our vector scheduling improves the performance because it can schedule not only based on data-dependencies but on loop structure or iteration conditions at the object code level. We compare the resulting schedules with those by software-pipelining techniques in the aspect of performance.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.7B
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• pp.647-659
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• 2003

LPM(Longest Prefix Matching)searching in If address lookup is a major bottleneck of IP packet processing in the high speed router. In the conventional lookup table for the LPM searching in CAM(Content Addressable Memory) the complexity of fast update take 0(1). In this paper, we designed pipeline architecture for fast update of 0(1) cycle of lookup table and high throughput and low area complexity on LPM searching. Lookup-table architecture was designed by CAM(Content Addressable Memory)away that uses 1bit RAM(Random Access Memory)cell. It has three pipeline stages. Its LPM searching rate is affected by both the number of key field blocks in stage 1 and stage 2, and distribution of matching Point. The RTL(Register Transistor Level) design is carried out using Verilog-HDL. The functional verification is thoroughly done at the gate level using 0.35${\mu}{\textrm}{m}$ CMOS SEC standard cell library.