• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.12A
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• pp.1160-1170
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• 2010

Existing multipath routing mechanism has much overhead to maintain the state of nodes on the multipath route and does not guarantees completely disjoint multipath construction from source to destination. In this paper, we propose an Explicit Disjoint Multipath (EDM) routing algorithm to enhance energy efficiency through removing the flooding mechanism for route discovery process, minimizing the number of nodes participating in route update and balancing the traffic load for entire network. EDM constructs logical pipelines which can create disjoint multipaths in logical way. Then it physically performs anchor node based geographic routing along the logical pipeline in order to build multipath to the destination. EDM can provide the distribution effect of traffic load over the network, help to balance the energy consumption and therefore extend the network lifetime.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.1B
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• pp.21-30
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• 2012

Sensor networks are composed of a great number of sensor nodes with constrained battery. Disjoint multipath scheme based flooding method has a merit that efficiently construct multipath in irregular networks, but causes lots of energy consumption in networks. Flooding method is not a suitable technology in wireless sensor networks with constrained battery. We introduce energy-efficient geographic routing scheme considered as an efficient, simple, and scalable routing protocol for wireless sensor networks. The geographic routing scheme on multipath generates a problem with a congestion. So we introduce the concept of multipath pipeline as a congestion avoidance strategy. But multipath pipelines have a big problem on the boundary of holes under irregular networks. We propose a novel disjoint multipath scheme as combined method with geographic routing scheme and hole detouring algorithm on multipath. A novel disjoint multipath scheme constructs disjoint multipath pipelines efficiently for reliability without a collision in irregular wireless sensor networks. Simulation results are provided to validate the claims.

• Proceedings of the Korea Information Processing Society Conference
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• 2010.11a
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• pp.1632-1634
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• 2010

고성능 재구성형 어레이 아키텍처는 애플리케이션에 내재된 병렬성을 충분히 활용하도록 풍부한 하드웨어 리소스로 구성되어 있다. 이러한 하드웨어 리소스는 소프트웨어 파이프라이닝 기반 코드할당 기법을 통하여 사용된다. 이러한 코드할당 기법은 기존의 소프트웨어 파이프라이닝 기법에 FPGA 에서의 라우팅 & 위치선정기법이 연결된 형식으로 구성된다. 이러한 기존의 연구들은 데이터 흐름 (data flow)을 단순한 형태로 가정하여 개발되었다. 따라서 루프 코드 펼침 (loop unrolling)에 따라서 발생되는 데이터 복사에 의한 흐름 (copy flow)은 코드 매핑할 때 고려하지 않기 때문에 소프트웨어 파이프라이닝 적용시 네트웍 리소스의 중복사용으로 인한 데이터 충돌문제(data congestion)로 Minimum Initiation Interval (MII)증가에 따르는 성능 저하가 발생할 수 있다. 본 연구에서는 다양한 데이터 복사 흐름까지 고려하도록 데이터 의존도 그래프 (Data Dependence Graph, DDG)를 확장하여 스케쥴링 단계에서 데이터 충돌 지연에 의한 MII 증가를 방지하여 최적의 시스템 성능을 얻도록 코드 할당 기법을 개발하였다.

• Journal of IKEEE
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• v.5 no.1 s.8
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• pp.24-34
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• 2001

IP address lookup is a major bottleneck of IP packet processing in high speed router. Existing IP lookup methods are focused only on lookup throughput without considering lookup table update. So their slow update can lead to lookup blocking or wrong routing decision based on obsolete routes. Especially existing IP lookup methods based on CAM(content addressable memory) have slow update of O(n) cycles in spite of their high throughput and low area complexity In this paper we proposes a new IP address lookup method based on pipelined CAM architecture(PICAM) with fast update of O(1) cycle of lookup table and high throughput and low area complexity.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.05a
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• pp.264-267
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• 2002

This paper presents the design of a pipelined virtual output queue routing engine for an advanced input-queued ATM switch, which has a serial cross bar structure. The proposed routing engine has been designed for wire-speed routing with a pipelined buffer management. It provides the tolerance of requests and grants data transmission latency between the routing engine and central arbiter using a new request control method that is based on a high-speed shifter. The designed routing engine has been implemented in a field programmable gate array (FPGA) chip with a 77MHz operating frequency, 16$\times$16 switch size, and 2.5Gbps/port speed.

• The Journal of the Korea Contents Association
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• v.13 no.2
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• pp.44-51
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• 2013

Routers should perform fast IP address lookup for Internet to provide high-speed service. In this paper, we present a hybrid parallel IP address lookup structure composed of four-stage pipeline. It achieves parallelism at low cost by using multiple SRAMs in stage 2 and partitioned TCAMs in stage 3, and improves the performance through pipelining. The smart distributor in stage 1 does not transfer any IP address identical to previous one toward the next stage, but only uses the result of the previous lookup. So it improves throughput of lookup by caching effects, and decreases the access conflict to TCAM bank in stage 3 as well. In the last stage, the reorder buffer rearranges the completed IP addresses according to the input order. We evaluate the performance of our parallel pipelined IP lookup structure comparing with previous hybrid structure, using the real routing table and traffic distributions generated by Zipf's law.

• Journal of KIISE:Computer Systems and Theory
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• v.29 no.1
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• pp.10-15
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• 2002

This paper proposes the Pipelined Broadcast that broadcasts a message of size m in O(m+n-1) time in an n-dimensional hypercube. It is based on the replication tree, which is derived from the reachable sets. It greatly improves the performance compared to Ho-Kao s algorithm with the time of O(m[n/log(n+1)]). The communication in the broadcast uses all-port wormhole router with message replication capability. This paper includes the algorithm together with performance comparisons to previous schemes in practical implementation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.05a
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• pp.394-397
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• 2003

In this paper, we describe the implementation of high performance buffer manager that is used in an advanced input-queued switch fabric. The designed buffer manager provides wire-speed cell/packet routing with low cost and tolerates the transmission pipeline latency of request and grant data. The buffer manager is implemented in a FPGA chip and supports the speed of OC-48c, 2.5Gbps per port.

• Journal of the Society of Naval Architects of Korea
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• v.43 no.2 s.146
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• pp.258-267
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• 2006

The present piping modeling method requires detailed inputs from a designer to generate a piping model, and thus it takes much time for the designer to perform such task. Moreover, the piping model has no relation with that of hull structure. Thus, it is time-consuming and requires much effort if design changes arise. In this study, a method that generates quickly many pipes using a pipe tray and a conversion method that converts automatically the pipes into objects related with the hull structure are proposed. A piping modeling system based on the proposed methods is developed. The applicability of the developed system is demonstrated by applying it to the generation of the piping model of a deadweight 300,000ton VLCC(Very Large Crude oil Carrier). The results show that the developed system can quickly generate the piping model in relation with the hull structure.