• Journal of KIISE:Computing Practices and Letters
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• v.11 no.1
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• pp.92-99
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• 2005

In this paper, we present a high-level design methodology applied on a network system-on-a-chip(SOC) using SystemC. The main target of our approach is to get optimum performance parameters for high network address translation(NAT) throughput. The Fast Ethernet media access controller(MAC) and its direct memory access(DMA) controller are modeled with SystemC in transaction level. They are calibrated through the cycle-based measurement of the operation of the real Verilog register transfer language(RTL). The NAT throughput of the model is within $\pm$10% error compared to the output of the real evaluation board. Simulation speed of the model is more than 100 times laster than the RTL. The validated models are used for intensive architecture exploration to find the performance bottleneck in the NAT router.

• Journal of KIISE:Computing Practices and Letters
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• v.12 no.2
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• pp.129-140
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• 2006

The existing CBD development methods deal with the analysis phase in a superficial manner. Applying such a superficial analysis to business applications with a number of subsystems makes analysis models be inconsistent with levels and styles, only depending on experiences of the analysts. This inconsistent analysis might cause more serious problems during the subsequent development phases, resulting in the failure of the projects. In this paper, we propose a rule-based analysis pattern that provides an analysis template for business applications. This pattern analyzes the concepts of business applications by using external events and internal rules that process the events. Employing this pattern, a huge business application can be developed by a couple of co-analysts who work together in a consistent and systematic manner. This paper also describes an efficient way to develop business components with the suggested analysis pattern using banking deposit case study through UML Components development process.