• Proceedings of the Korean Information Science Society Conference
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• 2004.10c
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• pp.496-498
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• 2004

트랜스코딩은 이미 압축된 비디오를 이질적인 클라이언트에게 적응적으로 전달하기 위한 해결책이다. 일반적으로, 계산량을 줄이기 위해서 제안된 트랜스코딩 기법들은 비디오 화질의 열화를 발생시키고 그와 반대의 경우는 많은 계산량을 초래한다. 이와 같은 계산량과 화질 사이의 문제를 해결하기 위해서 여러가지 측면이 연구되어 왔다. 하지만. 대부분의 연구가 트랜스코더 내부에 한정되어 있었고, 서버 측과의 상호작용을 통한 성능 향상에 대한 연구는 적었다. 멀티미디어 데이터를 전력과 성능이 낮은 단말기 또는 낮은 대역폭의 네트워크에 속한 이질적인 클라이언트에 서비스할 때 트랜스코더 자체의 해결 방안에 서버 측에의 특정 잡업을 추가할 경우 트랜스코더에서 실제 처리해야 하는 프레임의 개수를 줄일 수 있는 서비스 효율의 향상을 기대할 수 있다. 따라서 본 논문에서는 효율적인 트랜스코더와 서대 측 기반의 알고리즘을 함께 고려하여 계산 처리 과정을 줄일 수 있는 트랜스코더 시스템 구조를 제안한다.

• The KIPS Transactions:PartB
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• v.12B no.4 s.100
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• pp.451-458
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• 2005

The transcoding is a solution which is able to adapt to heterogeneous clients of requesting a different playback rate of multimedia data. Thus, The transcoding needs decoding and encoding. In general, previous studies to reduce complexity have a problem, the degradation of visual quality On the contrary, previous studies to reduce the degradation of visual quality lead to heavy computation. Thus, many researchers have studied a solution between the complexity and the degradation of visual quality. But until now, most researches of this region have dealt with the transcoder itself, such researches about a server's assistance to improve the performance of transcoder is rarely studied. In case of servicing multimedia data to heterogeneous clients which have low capabilities, the assistance of server side is able to reduce frames with processing in the transcoder and improve the performance of the transcoder. Thus in this paper, we propose the frame-skipping transcoder system architecture that takes into consideration transcoder and server side to reduce the complexity of the transcoder.

• The KIPS Transactions:PartB
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• v.12B no.3 s.99
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• pp.313-322
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• 2005

In order to access digital items in a server via ubiquitous devices, the digital items should be adapted according to the system environment, device characteristics and user preferences. In ubiquitous environment, those device-dependent adaptation requirements are not statically determined and not predictable. Therefore an application specific adaptation mechanism can not be applied to a general digital item adaptation engine. In this paper, we propose an application independent digital item adaptation architecture which has a set of minimal transcoders, transcoding path generator for a required adaptation requirement, and adaptation scheduler. And a CFG based method of finding a sequence of multiple unit transcoders called a transcoding path Is described in detail followed by experimental results.

• The KIPS Transactions:PartB
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• v.12B no.6 s.102
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• pp.637-646
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• 2005

Most of the multimedia contents for DBM services art provided as MPEG-2 bit streams. However, they have to be transcoded to H.264 bit streams for practical services because the standard video codec for DMB is H.264. The existing transcoder architecture is Cascaded Pixel-Domain Transcoding Architecture, which consists of the MPEG-2 dacoding phase and the H.264 encoding phase. This architecture can be easily implemented using MPEG-2 decoder and H.264 encoder without source modifying. However. It has disadvantages in transcoding time and DCT-mismatch problem. In this paper, we propose two kinds of transcoder architecture, DCT-OPEN and DCT-CLOSED, to complement the CPDT architecture. Although DCT-OPEN has lower PSNR than CPDT due to drift problem, it is efficient for real-time transcoding. On the contrary, the DCT-CLOSED architecture has the advantage of PSNR over CPDT at the cost of transcoding time.

• The KIPS Transactions:PartB
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• v.17B no.1
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• pp.31-36
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• 2010

After the launch of MPEG-2, it is widely used in multimedia applications like a Digital-TV or a DVD. Then, After the launch of H.264 at 2004, it has been expected to replace MPEG-2 and services IPTV and DMB. As we have been used to MPEG-2 devices by this time, we can not access H.264 Broadcast with MPEG-2 device. So We propose a new approach to transcode H.264 video into MPEG-2 form which can facilitate to display H.264 video with MPEG-2 device. To reduce the quality loss by transcoding, we use CPDT(Cascaded Pixel Domain Transcoder) structure. And to minimize processing time, SKIP block, INTRA block and motion vectors obtain from decoding process is employed for transcoding. we use BMA(Boundary Matching Algorithm) to select only one from candidate motion vectors. Experimental results show a considerable improved PSNR with reduction in processing time compared with existing methods.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.4 no.1
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• pp.9-16
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• 2011

In this paper, we propose an efficience transcoder architecture to support a simutaneous multibitrate output. First, we discuss about some architectures to realize this feature. Next, we explain the proposed architecture, it shares not only VLD-IQ but alse Q-VlD which have the same quantization step sizes each other. We anlyze the numbers of Q-VLC times per on Macroblock to the investigate an effect of sharing, and evaluate its computation complexity. The result of simulation, that complexity has an upper limit and it cn support any numbers of bitstream by about 3~6 times complexity than single output.

• Proceedings of the Korea Information Processing Society Conference
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• 2006.05a
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• pp.123-126
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• 2006

멀티미디어 홈 네트워크 환경을 위해서는 A/V(Audio/Video)데이터의 실시간 전송에 유리한 IEEE1394 네트워크와 이동성을 편리하게 지원하고, 홈 외부로의 전송에 적합한 이더넷의 상호 연동 서비스가 필요하다. 따라서 본 논문은 가정내의 IEEE1394 기반 A/V 장치에서 홈 내부 및 외부의 이더넷 기반 모바일 장치로 멀티미디어 데이터를 전송하고, 인터넷의 멀티미디어 데이터를 IEEE1394 기반 A/V 장치로 전송하는 홈 게이트웨이의 구조를 제안한다. 멀티미디어 데이터의 실시간 전송을 위해 DV to MPEG4 트랜스코더를 DV, MPEG4 코덱을 통해 구현하였고, IEEE1394 네트워크와 이더넷 사이의 멀티미디어 데이터 전송 및 제어를 위해 스트리밍 서버와 MPEG4 코덱을 내장한 클라이언트, 그리고 IEC61883 규격을 이용한 IEEE1394 장치 제어 모듈을 제작하였다.

• The Transactions of the Korea Information Processing Society
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• v.1 no.4
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• pp.469-478
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• 1994

In this paper, a high speed, high resolution information processing digital- analog converter was designed for high definition color graphic, digital image signal processing, HDTV. For high speed operation, matrix type current cell array, latch which is not use pipelined, and two dimensional structure decoder using transmission gate were designed. It is adopted to fast-conversion, low-power implementation and exhibited high performance at linearity and accuracy. To reduce silicon area and to maintain resolution, current cell array composed of weighted and non-weighted current cells. In this paper, deglitching current cell design for high accuracy, new switching algorithm assert to reduce switching error. It's This circuit dissipates 130W with a 5-V power supply, and operate above 100MHz with 10 bit resolution.