• Title/Summary/Keyword: 클럭 특성

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Curvature stroke modeling for the recognition of on-line cursive korean characters (온라인 흘림체 한글 인식을 위한 곡률획 모델링 기법)

  • 전병환;김무영;김창수;박강령;김재희
    • Journal of the Korean Institute of Telematics and Electronics B
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    • v.33B no.11
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    • pp.140-149
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    • 1996
  • Cursive characters are written on an economical principle to reduce the motion of a pen in the limit of distinction between characters. That is, the pen is not lifted up to move for writing a next stroke, the pen is not moved at all, or connected two strokes chance their shapes to a similar and simple shape which is easy to be written. For these reasons, strokes and korean alphabets are not only easy to be changed, but also difficult to be splitted. In this paper, we propose a curvature stroke modeling method for splitting and matching by using a structural primitive. A curvature stroke is defined as a substroke which does not change its curvanture. Input strokes handwritten in a cursive style are splitted into a sequence of curvature strokes by segmenting the points which change the direction of rotation, which occur a sudden change of direction, and which occur an excessive rotation Each reference of korean alphabets is handwritten in a printed style and is saved as a sequence of curvature strikes which is generated by splitting process. And merging process is used to generate various sequences of curvature strikes for matching. Here, it is also considered that imaginary strokes can be written or omitted. By using a curvature stroke as a unit of recognition, redundant splitting points in input characters are effectively reduced and exact matching is possible by generating a reference curvature stroke, which consists of the parts of adjacent two korean alphasbets, even when the connecting points between korean alphabets are not splitted. The results showed 83.6% as recognition rate of the first candidate and 0.99sec./character (CPU clock:66MHz) as processing time.

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Performance Analysis of Slave-Side Arbitration Schemes for the Multi-Layer AHB BusMatrix (ML-AHB 버스 매트릭스를 위한 슬레이브 중심 중재 방식의 성능 분석)

  • Hwang, Soo-Yun;Park, Hyeong-Jun;Jhang, Kyoung-Son
    • Journal of KIISE:Computer Systems and Theory
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    • v.34 no.5_6
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    • pp.257-266
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    • 2007
  • In On-Chip bus, the arbitration scheme is one of the critical factors that decide the overall system performance. The arbitration scheme used in traditional shared bus is the master-side arbitration based on the request and grant signals between multiple masters and single arbiter. In the case of the master-side arbitration, only one master and one slave can transfer the data at a time. Therefore the throughput of total bus system and the utilization of resources are decreased in the master-side arbitration. However in the slave-side arbitration, there is an arbiter at each slave port and the master just starts a transaction and waits for the slave response to proceed to the next transfer. Thus, the unit of arbitration can be a transaction or a transfer. Besides the throughput of total bus system and the utilization of resources are increased since the multiple masters can simultaneously perform transfers with independent slaves. In this paper, we implement and analyze the arbitration schemes for the Multi-Layer AHB BusMatrix based on the slave-side arbitration. We implement the slave-side arbitration schemes based on fixed priority, round robin and dynamic priority and accomplish the performance simulation to compare and analyze the performance of each arbitration scheme according to the characteristics of the master and slave. With the performance simulation, we observed that when there are few masters on critical path in a bus system, the arbitration scheme based on dynamic priority shows the maximum performance and in other cases, the arbitration scheme based on round robin shows the highest performance. In addition, the arbitration scheme with transaction based multiplexing shows higher performance than the same arbitration scheme with single transfer based switching in an application with frequent accesses to the long latency devices or memories such as SDRAM. The improvements of the arbitration scheme with transaction based multiplexing are 26%, 42% and 51%, respectively when the latency times of SDRAM are 1, 2 and 3 clock cycles.