• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.12
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• pp.1983-1993
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• 1993

A power-reduction technique for full-flash A/D converters is proposed. As the resolution of a full-flash A/D converter increases linearly, the number of comparators increases exponentially. The power dissipation is generally larger than other A/D converter architectures because there are many comparators, and they are operating continuously. In this proposed architecture, only a selected number of conmarators are made to operate instead of activating all the comparators of the full-flash A/D convertor. To determine whichcomparators should be activated, voltage levelfider circuits are used. A new clock driver is developed to suppress the dynamic glitch noise which is fed back into the input stage of the comparator. By using this clock driver, the glitch noise in the current source is reduced to one fourth of that when the typical clock signal is applied. The proposed architecture has been implemented with 1.2 m 5GHz BiCMOS technology. The maximum conversion speed is 350Msamples/s. and dissipates only 900mW.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.8
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• pp.1283-1291
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• 2002

In this paper, the PLL driven by the DDFS is designed on the schematic using the Q-logic cell based library and is implemented using FPGA QL32 x16B. The measurement results of the frequency synthesizer switching speed were agreement with a register. The simulated results show that the clock delay was generated after eleven clock and if input is random, It has influence on output DA converter has to be very extensive. Therefore, the DDFS used noise shaper to drive PLL by regular interval for input state. Also the bandwidth of DA converter very extensive, the simulation shows that the variation of small input control word is better than the switching speed of PLL.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.135-139
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• 2008

In this paper, tunable SC(switched capacitor) 2nd order bandpass $\Sigma-\Delta$(Sigma-Delta) modulator with novel architecture that can adjust the IF band center frequency by one coefficient value is proposed for data conversion in the IF(Intermediate Frequency) band. Its architecture can optionally adjust all the 2nd order noise transfer function in comparison with the conventional architecture. In order to adjust the center frequency, the conventional architecture needs the two variable coefficient values, basic clock and eight clocks. On the other hand, the proposed architecture can adjust the center frequency by one variable coefficient value and basic clock only.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.3
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• pp.333-341
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• 2015

In this paper, a 0.5~4 GHz frequency synthesizer having good phase noise performance is proposed. Wideband output frequencies of the synthesizer were synthesized using DDS(Direct Digital Synthesizer) and analog direct frequency synthesis technology in order to obtain fast settling time. Also in order to get good phase noise performance, 2.4 GHz DDS clock was generated by VCO(Voltage Controlled Oscillator) which was locked by the 100 MHz reference oscillator using SPD(Sample Phase Detector). The phase noise performance of wideband frequency synthesizer was estimated and the results were compared with the measured ones. The measured phase noise of the frequency synthesizer was less then -121 dBc @ 100 kHz at 4 GHz.

• The Journal of the Korea Contents Association
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• v.9 no.7
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• pp.76-85
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• 2009

UWB signal with high resolution capability can be used to estimate ranging and positioning in wireless personal area network. The node works on its local clock and the frequency differences of nodes have serious affects on ranging algorithms estimating locations of mobile nodes. The low rate UWB, IEEE802.15.4a, describes asynchronous two way ranging methods such as TWR and SDS-TWR working without any additional network synchronization, but the algorithms can not eliminate the effect of clock frequency differences. Therefore, the mechanisms to characterize the crystal difference is essential in typical UWB PHY implementations. In high rate UWB, characterizing of crystal offset with tracking loop is not required. But, detection of the clock frequency offset between the local clock and remote clock can be performed if there is little noise induced jitter. In this paper, we complete related ranging equations of high rate UWB based on TWR with relative frequency offset, and analyze a residual error in the ideal equations. We also evaluate the performance of the relative frequency offset algorithm by simulation and analyze the ranging errors according to the number of TWR to compensate coarse clock resolution. The results show that the relative frequency offset compensation and many times of TWR enhance the performance to converge to a limited ranging errors even with coarse clock resolutions.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.14 no.2
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• pp.135-140
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• 2014

In this paper, we describe the contents of noise characteristic enhancement using digital filtering to the motion vector in the pattern noise of optical mouse. The designed circuit is implemented to enhance the smoothing and trembling with filtering and averaging of x, y motion vector before PS2 or USB output. The function is verified by using FPGA and the performance is measured by the fabricated chip using $0.35{\mu}m$ standard CMOS process. The system clock is 6MHz and the motion vector has the range of +6 to -6 per 1/1700sec. It is tested using the Cartesian robot to measure the noise characteristic enhancement.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.7A
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• pp.678-685
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• 2007

We implemented the network synchronization equipment for the optical transmission platform or next generation Packet/TDM(Time Division Multiplexing) data converged switching system and then, presented an impact of wander generation on the NG-SDH optical transmission network.

• Proceedings of the Acoustical Society of Korea Conference
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• spring
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• pp.61-64
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• 2004

본 논문에서는 저전송율 음성부호화기인 2.4kbps MELP(Mixed Excitation Linear Prediction) 보코더를 TI(Texas Instruments) 사의 고정소수점 DSP인 TMS 320VC5510을 이용하여 실시간 구현한 결과를 제시한다. MELP 보코더는 전통적인 LPC 합성방식에 기반한 것으로, 2.4kbps LPC 보코더가 여기신호를 유성음 구간에 대해서는 펄스열로, 무성음 구간에 대해서는 백색잡음 신호로 단순화시켜 합성함으로써 음질이 저하되거나 buzz 현상이 나타나는 단점을 적절히 혼합된 형태의 여기신호를 사용함으로써 보완한 것이다. DDVPC(Defense Digital Voice Processing Consortium)에서 제공하는 ANSI C 소스 코드를 이용하여 TMS320VC5510 DSK에서 실시간 동작이 가능하도록 최적화 작업을 수행하였으며, 구현된 MELP 보코더는 프로그램 메모리 46.5 kbyte와 데이터 메모리 57.9 kbyte를 가지며, 22.5ms의 한 프레임을 처리하는데 1326531 클럭(6.6 ms)이 소요되었다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.10a
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• pp.176-179
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• 2000

The PLL synthesizer is used often in communication system due to several merits, such as broad bandwidth, high accuracy and stability of frequency. But it is difficult to use in current digital communication systems that need frequency hopping at a high speed because of its long frequency hopping time. In this paper, we designed frequency synthesizer that generate the clock frequency randomly at a high speed using the DDS technology and is applied to the pattern generator systemfor for digital image.

• Proceedings of the KIEE Conference
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• 2015.07a
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• pp.1251-1252
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• 2015

본 논문에서는 자기 공명 방식 무선전력전송시스템의 전자파 노이즈 원을 분석하기 위해서 근역장 측정 시스템을 이용하여 PCB 회로에 분포하는 근역장 분포를 측정하였다. 측정된 시료는 6.78 MHz를 사용하는 시스템으로 자기 공명 방식으로 에너지를 전송하고 있다. 주 전자파 노이즈 원으로 6.78 MHz의 공진 주파수의 고조파와 시스템에 안정적인 전압을 공급하기 위해 사용되는 레귤레이터의 내부 클럭 신호의 고조파가 많이 발생하고 있다. 이들 고조파 성분은 전 대역의 주파수 영역에 넓게 분포하는 것으로 나타났다.