• Information and Communications Magazine
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• v.10 no.5
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• pp.53-70
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• 1993

위상 복원 문제는 어떤 신호의 푸리에 변환의 크기로부터 푸리에 위상, 또는 그 신호 자체를 구하는 문제로서 신호처리, 천문학, X-선 결정학, 전자현미경학, 광학, synthetic aperture radar 등과 같은 많은 물리학의 분야에서 일어난다. 일반적으로, 이 위상 복원 문제는 유일한 해를 갖지 않기 때문에, 이 문제를 풀기 위하여 사전 정보로 주어지는 원하는 신호의 성질을 제한조건으로 주어 이 문제가 유일한 해를 갖도록 한 뒤 이 원하는 신호를 구하는 방법을 사용해왔다. 이 논문에서는 위상 복원 문제를 소개하고, 이 문제의 중요성, 기본 이론 등을 알아보고, 지금까지 제안이 되었던 방법들을 분야별로 묶어 신호처리의 관점에서 소개한다. 먼저 수학적인 기초에 대하여 소개하고, 푸리에 변환의 크기를 보존하는 변환들에 대하여 알아본 뒤, 위상 복원 문제를 풀기 위하여 제안이 되었던 방법들을 1)하나의 푸리에 변환의 크기가 주어졌을 때의 위상 복원, 2)더해지는 기준 신호가 있을 때의 위상 복원, 3)곱해지는 신호(윈도우)를 이용한 위상 복원으로 나누어 소개한다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.2
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• pp.339-344
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• 2017

A novel structure of phase locked loop (PLL) which has small size and fast locking time with Early-late detector, Duty-rate modulator, and Lock status indicator (LSI) is proposed in this paper. The area of loop filter usually occupying the larger portion of the chip is minimized using a single small capacitor. While the conventional PLL with a single capacitor loop filter cannot work stably, the proposed PLL with two charge pumps works stably because the output voltage waveform of the proposed a single capacitor loop filter is the same as the output voltage waveform of the conventional 2nd-order loop filter. The two charge pumps are controlled by the Early-late detector which detects early-late status of UP and DN signals, and Duty-rate modulator which generates a steady duty-rate signal. Fast locking time is achieved using LSI. It has been simulated and proved by HSPICE in a CMOS $0.18{\mu}m$ 1.8V process.

• Journal of the KSME
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• v.33 no.12
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• pp.1076-1085
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• 1993

레이저광이 가지는 지향성, 단색성, 공간적 집속성 등의 성질을 이용하는 각종 측정장치는 광섬 유의 발달과 새로운 신호처리계의 개발로 그 적용 범위가 점점 확대되고 있다. 레이저 도플러 신호의 위상차를 이용하여 운동상태의 입자의 크기와 속도를 동시에 측정할 수 있는 측정장치가 80년대에 실용화되어 캐비테이션, 분무노즐, 기름버너, 엔진연소 등 많은 분야에서 다양하게 사 용되고 있다. 이 측정방법은 Durst와 Zare에 의해 도플러 신호의 위상과 입자의 크기는 선형적인 함수 관계가 있음이 밝혀진 이래, Bachalo, Buchhave, Knuhfsen과 Olldag 등에 의해 급속히 발 전되었다. 현재 국내에도 덴마크의 단텍사, 미국의 에어로메트릭스사 등에서 개발한 장비가 3-4 기관에서 사용되고 있다. 이 글에서는 위상도플러법에 의한 입자의 크기측정에 관한 기초 이론을 참고문헌을 인용하여 설명하고, 단텍사에서 개발한 위상도플러 측정장치인 입자운동 해석장치 (PDA)를 사용하여 본 연구실에서 실험한 버너용 압력분사식 노즐에서 분사된 액적들의 국소부분 거동에 대해 소개하기로 한다.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.2
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• pp.123-128
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• 2020

A low phase noise phase locked loop (PLL) with negative feedback loop including frequency variation sensing circuit (FVSC) has been proposed. The FVSC senses the frequency variation of voltage controlled oscillator output signal and controls the volume of electric charge in loop filter capacitance. As the output frequency of the phase locked loop increases, the FVSC reduces the loop filter capacitor charge. This causes the loop filter output voltage to decrease, resulting in a phase locked loop output frequency decrease. The added negative feedback loop improves the phase noise characteristics of the proposed phase locked loop. The size of capacitance used in FVSC is much smaller than that of loop filter capacitance resulting in no effect in the size of the proposed PLL. The proposed low phase noise PLL with FVSC is designed with a supply voltage of 1.8V in a 0.18㎛ CMOS process. Simulation results show the jitter of 273fs and the locking time of 1.5㎲.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.71-77
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• 2009

A novel phase-locked loop(PLL) architecture with multiple charge pumps for fast locking has been proposed. The proposed PLL has three charge pumps. The effective capacitance and resistance of the loop filter can be scaled up/down according to the locking status by controlling the direction and magnitude of each charge pump current. The fast locking PLL that changes its loop bandwidth through controlling charge pumps depending on locking status has been designed. The capacitor usually occupying the larger portion of the chip is also minimized with the proposed scheme. Therefore, the PLL size of $990{\mu}m\;{\times}\;670{\mu}m$ including resistors and capacitors at the bandwidth of 29.9KHz has been achieved. It has been fabricated with 3.3V $0.35{\mu}m$ CMOS process. The locking time is less than $6{\mu}s$ with the measured phase noise of -90.45dBc/Hz @1MHz at 851.2MHz output frequency.

• Journal of the Korean Society for Nondestructive Testing
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• v.27 no.4
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• pp.321-327
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• 2007

In lock-in thermography, a phase difference between the defect area and the healthy area indicates the qualitative location and size of the defect. To accurately estimate these parameters, the shearing-phase technique has been employed which gives the shearing-phase distribution. The shearing-phase distribution has maximum, minimum, and zero points that help determine quantitatively the size and location of the subsurface defect. In experiment, the proposed technique is verified with artificial specimen and these related factors are analyzed.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.5
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• pp.531-537
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• 2018

A novel PLL with a delta-sigma modulator and a spur reduction circuit is proposed. delta-sigma modulator makes the LF remove noise easily by moving the spur noise to a higher frequency band. Therefore, the magnitude of spur can be reduced the reasonable bandwidth. The spur reduction circuit reduces the spur size by reducing the LF voltage change generated during the period of reference signal. The spur reduction circuit is designed as simple as possible not to increase the size of PLL. The proposed PLL with the previous two techniques is designed with a supply voltage of 1.8V in a 0.18um CMOS process. Simulation results show an almost 20dB reduction in the magnitude of spur. The spur reduced PLL can be used in narrow bandwidth communication system.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.6
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• pp.651-657
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• 2018

A novel PLL with a delta-sigma modulator and a spur reduction circuit is proposed. delta-sigma modulator makes the LF remove noise easily by moving the spur noise to a higher frequency band. Therefore, the magnitude of spur can be reduced the reasonable bandwidth. The spur reduction circuit reduces the spur size by reducing the LF voltage change generated during the period of reference signal. The spur reduction circuit is designed as simple as possible not to increase the size of PLL. The proposed PLL with the previous two techniques is designed with a supply voltage of 1.8V in a 0.18um CMOS process. Simulation results show an almost 20dB reduction in the magnitude of spur. The spur reduced PLL can be used in narrow bandwidth communication system.

• The Journal of the Acoustical Society of Korea
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• v.19 no.3
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• pp.86-91
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• 2000

In this paper, we will discuss the characteristics of the magnitude and the phase of the piano sound in frequency domain by using the FFT(Fast Fourier Transform). The method deciding the parameters representing those sounds through the mathematical model is described. We used the curve fitting method for the modeling of the harmonic part of the sound including the fundamental frequency in order to minimize the errors between original sounds and modeled sounds. furthermore, we used the line segment approximation method for the modeling of the noise part around fundamental frequency. We also applied the same method for the phase model and could get the modeled sound to be similar to the original sound using the parameters. Therefore the high compression ratio comparing the modeled sound to the original sound is achieved.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.8
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• pp.1068-1075
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• 2018

In this paper, a novel PLL has been proposed that reduces the size of the loop filter while suppressing spur by using a VCO with two inputs. Through the stability analysis according to the operating status, the PLL is designed to operate stably after the phase fixing. The capacitor of loop filter usually occupies larger area of PLL. It is a VCO that can reduce the size of the loop filter by increasing the effective capacitance of the capacitor through the simultaneous charge and discharge operation by two charge pumps and has two signals operating in opposite phases. The settling time of set to $80{\mu}s$ approximately by using a LSI(Locking Status Indicator) indicating the phase locking status. The proposed PLL is designed using a supply voltage of 1.8V and a $0.18{\mu}m$ CMOS process.