• Title/Summary/Keyword: 커시브

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Design of Graphic Generator for Driving HUD(Head-Up Display) and MFD(Multi-Function Display) (전방시현기 및 다기능시현기 구동을 위한 그래픽 영상생성기 설계 연구)

  • 황상현;이재억;박덕배
    • Journal of the Korea Institute of Military Science and Technology
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    • v.5 no.2
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    • pp.72-82
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    • 2002
  • This paper presents the design technology of a Graphic Generator which drives the embedded aircraft display equipments such as HUD(Head-Up Display) and MFD (Multi-Function Display) those provide pilot with the most important mission information. The main issue of this design is how we can implement the real-time embedded graphic generator using a general purpose processor as a substitute for the obsolete the production of specific graphic processor in the military market. So we proposed two kinds of method that one is a software solution so called graphic kernel system, interpreting the display file, controlling the graphic system and pre-processing graphic primitives, the other is a hardware solution so called graphic engine, interpreting passed commands through the graphic kernel system, post-processing the looping calculation taking much of time as implemented by software. We have tested and verified the functionalities and the required performance of Graphic Generator.

A study on the parallel processing of the avionic system computer using multi RISC processors (다중 RISC 프로세서를 이용한 항공전자시스템컴퓨터 병렬처리기법 연구)

  • Lee, Jae-Uk;Lee, Sung-Soo;Kim, Young-Taek;Yang, Seung-Yul;Kim, Bong-Gyu;Hwang, Sang-Hyun;Park, Deok-Bae
    • Journal of the Korean Society for Aeronautical & Space Sciences
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    • v.30 no.7
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    • pp.144-149
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    • 2002
  • This paper presents a technique for real time multiprocessor parallel processing to develop an avionic system computer(ASC) which integrates the avionics control, navigation and fire control, cursive and raster graphic symbol generation into one line replaceable unit. The proposed method has optimal performance by adopting a logically asymmetric structure between four 32bit RISC processors based on the master-slave multiprocessing, a tightly coupled interaction level with the time shared common bus and global memory, and an efficient bus arbitration algorithm. The ASC has been verified through a series of flight tests. The relevant tests also have been rigorously conducted on the prototype ASC such as electrical test, environmental test, and electromagnetic interference test.