• Korean Journal of Optics and Photonics
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• v.32 no.5
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• pp.230-234
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• 2021

Relief of thermal stress has received great attention, to improve the beam quality and stability of high-power laser diodes. In this paper, we investigate a microtrench structure engraved around a laser-diode chip-on-submount (CoS) to relieve the thermal stress on a laser-diode bar (LD-bar), using the SolidWorks® software. First, we systematically analyze the thermal stress on the LD-bar CoS with a metal heat-sink holder, and then derive an optimal design for thermal stress relief according to the change in microtrench depth. The thermal stress of the front part of the LD-bar CoS, which is the main cause of the "smile effect", is reduced to about 1/5 of that without the microtrench structure, while maintaining the thermal resistance.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.4
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• pp.149-154
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• 2018

This paper describes the fabrication and heat transfer property of 50 watts rated LED array module where multiple chips are mounted on chip-on-board type ceramic-metal hybrid substrate with high heat dissipation property for high power street and anti-explosive lighting system. The high heat transfer ceramic-metal hybrid substrate was fabricated by conformal coating of thick film glass-ceramic and silver pastes to form insulation and conductor layers, using thick film screen printing method on top of the high thermal conductivity aluminum alloy heat-spreading panel, then co-fired at $515^{\circ}C$. A comparative LED array module with the same configuration using epoxy resin based FR-4 PCB with thermalvia type was also fabricated, then the thermal properties were measured with multichannel temperature sensors and thermal resistance measuring system. As a result, the thermal resistance of the ceramic-metal hybrid substrate in the $4{\times}9$ type LEDs array module exhibited about one third to the value as that of FR-4 substrate, implying that at least triple performance of heat transfer property as that of FR-4 substrate was realized.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.93-100
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• 2009

This paper presents a step up four channel DC-DC converter using charge pump voltage doubler structure. Our goal is to design and implement DC-DC converter for capacitive SP4T RF MEMS switch in front end module in wireless transceiver system. Charge pump structure is small and consume low power 3.3V input voltage is boosted by DC-DC Converter to $11.3{\pm}0.1V$, $12.4{\pm}0.1V$, $14.1{\pm}0.2V$ output voltage With 10MHz switching frequency. By using voltage level shifter structure, output of DC-DC converter is selected by 3.3V four channel selection signals and transferred to capacitive MEMS devices. External passive devices are not used for driving DC-DC converter. The total chip area is $2.8{\times}2.1mm^2$ including pads and the power consumption is 7.52mW, 7.82mW, 8.61mW.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.10
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• pp.159-168
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• 2012

In this paper, a W-band single-chip receiver MMIC for FMCW(Frequency-modulated continuous-wave) radar is presented using $0.15{\mu}m$ GaAs pHEMT technology. The receiver MMIC consists of a 4-stage low noise amplifier(LNA), a down-converting mixer and a 3-stage LO buffer amplifier. The LNA is designed to exhibit a low noise figure and high linearity. A resistive mixer is adopted as a down-converting mixer in order to obtain high linearity and low noise performance at low IF. An additional LO buffer amplifier is also demonstrated to reduce the required LO power of the W-band mixer. The fabricated W-band single-chip receiver MMIC shows an excellent performance such as a conversion gain of 6.2 dB, a noise figure of 5.0 dB and input 1-dB compression point($P_{1dB,in}$) of -12.8 dBm, at the RF frequency of $f_0$ GHz, LO input power of -1 dBm and IF frequency of 100 MHz.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.117-117
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• 2009

최근 고집적화 구조는 저항(resistance)과 정전용량 (capacitance)에 의한 신호 지연 (RC delay) 증가로 인한 혼선 (cross-talk noise)과 전력소모 (power dissipation)등의 문제를 발생시킨다. 칩 성능에 영향을 미치는 제한인자를 최소화하기 위해서는 저저항 배선 금속과 저유전상수 (low-k)의 층간 절연막 (IMD, intermetal dielectric) 물질이 필요하다. 최근 PECVD (plasma enhanced chemical vapor deposition)를 이용하여 증착시킨 유기살리케이트 (OSG, organosilicate glass)는 가장 유망한 저유전상수 물질로 각광받고 있다. 본 연구에서는 제일원리 연구를 통하여 OSG의 전구체 중에 하나인 DEMS 문자를 모델링하고, 에너지적으로 가장 안정한 구조를 찾아서 각 원자 간의 결합에 따른 해리에너지 (dissociation energy)를 계산하고, DEMS가 H-terminated Si 표면과 반응하는 기구에 대해 고찰하였다. 최적화된 DEMS 분자의 구조를 찾았고 DEMS 분자가 결합이 깨져 조각 분자군으로 될 때의 에너지들을 계산하였다. 계산된 해리에너지로부터 DEMS 분자의 O 원자와 C분자의 결합이 깨져서 $C_2H_5$를 조각 분자군으로 생성할 확률이 총 8가지의 경우에서 가장 높다는 것을 알 수 있었다. 8 가지의 해리된 DEMS 조각 분자군들이 H-terminated Si 표면과 반응할 때의 반응에너지를 계산한 결과 표면의 Si 원자와 DEMS 분자에서 $C_2H_5$가 해리되어 생성된 조각 분자군의 O 원자가 결합을 하고 부산물로 $C_2H_6$를 생성하는 반응이 가장 선호된다는 것을 알 수 있었다. DEMS 분자로 증착시킨 OSG에 대하여 제일원리법을 이용하여 계산한 연구는 보고된 바 없기 때문에, DEMS 분자의 각 원자 간의 해리에너지와 Si 기판과의 반응에너지는 추후 연구개발의 중요한 기초 자료가 될 수 있다.

• Journal of Sensor Science and Technology
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• v.8 no.1
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• pp.38-44
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• 1999

In this paper, we have constructed a self-diagnostic circuit which could detect erroneous signals in most cases that a eight-beam piezoresistive accelerometer were destroyed more than its one beam. To confirm the function of the circuit, PSPICE simulation was carried out. An IC chip was fabricated with a layout of KA 324 amplifier using a bipolar standard processing. After a package of the chip was sealed using a plastic package with 24 pins, the self-diagnostic characteristics were investigated. Then, the measured self-diagnostic characteristics of the circuit were compared with the PSPICE simulated result.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.179-179
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• 2008

$BaTiO_3$를 기본조성으로 하는 PTC 써미스터는 Curie 온도이상에서 저항이 급격히 상승하는 산화물 반도체 세라믹이다. 이러한 성질을 이용하여 degaussing 소자, 정온 발열체, 온도센서, 전류 제한소자 등 상업적으로 여러 분야에서 연구되고 있다. 또한 원가절감 등을 위하여 Ni 내부전극을 사용하여 환원 분위기에서 소결하는 칩 타입에 대한 연구가 진행되고 있다. 본 연구에서는 Sm 함량(0.1at%~1.0at%)을 달리한 $BaTiO_3$(Si, Mn, Ca) 계를 선택하여 3%$H_2/N_2$ 분위기에서 1200~$1260^{\circ}C$, 2h 소결한 후 공기 중에서 재산화 처리하고 재산화 시간에 따른 PTC 특성 변화에 대하여 고찰하였다. 재산화 온도와 시간은 각각 $800^{\circ}C$와 0.5h~10h으로 하였다. Sm 함량을 달리하여 환원 분위기에서 소결한 시편의 미세구조와 PTC 특성과의 상관관계를 관찰한 결과, 소결온도가 낮을수록 PTC 특성은 좋아졌으며, 상온 비저항은 Sm 함량이 높아질수록 낮아졌다. 또한 Sm 함량이 높아질수록 jumping ratio$(R_{max}/R_{25^{\circ}C})$는 낮아졌다. 재산화 시간에 따른 PTC 특성은 다소 떨어졌지만 소결온도에 따라 달리 나타났다. Jumping ratio$(R_{max}/R_{25^{\circ}C})$는 Sm을 0.7 at% 첨가한 계에서 재산화를 1시간 처리한 시편에서 가장 우수하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.71-77
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• 2009

A novel phase-locked loop(PLL) architecture with multiple charge pumps for fast locking has been proposed. The proposed PLL has three charge pumps. The effective capacitance and resistance of the loop filter can be scaled up/down according to the locking status by controlling the direction and magnitude of each charge pump current. The fast locking PLL that changes its loop bandwidth through controlling charge pumps depending on locking status has been designed. The capacitor usually occupying the larger portion of the chip is also minimized with the proposed scheme. Therefore, the PLL size of $990{\mu}m\;{\times}\;670{\mu}m$ including resistors and capacitors at the bandwidth of 29.9KHz has been achieved. It has been fabricated with 3.3V $0.35{\mu}m$ CMOS process. The locking time is less than $6{\mu}s$ with the measured phase noise of -90.45dBc/Hz @1MHz at 851.2MHz output frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.3
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• pp.18-24
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• 2011

This paper presents that the yield strength of the pressure sensor with a double boss diaphragm structure can be improved as the grooves are formed at the corner of the diaphragm bridge. Generally the boss structure is widely used for the low-pressure sensor, of which the sensitivity is not enough in case of the small diaphragm size limited by a chip size constraint. The double boss structure pressure sensor exhibits a great sensitivity, but suffers from the low yield strength problem due to the high stress occurred at the corner of the diaphragm bridge to be limited in the operating range. ANSYS simulation is performed by changing the length of the groove from 0.5${\mu}m$ to 10${\mu}m$ at the corner of the diaphragm bridge of the double boss structure pressure sensor. The maximum stress is analyzed at the corner of the diaphragm bridge, the edge of the diaphragm bridge, and the position of the piezoresistive sensor. Consequently, in case the length of the groove from the edge of the diaphragm is 6${\mu}m$ or greater, the stress occurred in the corner of the bridge is less than the stress acting on a piezoresistive element.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.10-15
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• 2008

In this paper, a new NMOS gate cross-connected current-mirror type bridge rectifier for UHF RFID applications is presented. The DC converting characteristics of the proposed rectifier are analyzed with the high frequency equivalent circuit and the gate capacitance reduction technique for reducing the gate leakage current due to the increasing of operating frequency is also proposed theoretically by circuitry method. As the results, the proposed rectifier shows nearly same DC output voltages as the existing NMOS gate cross-connected rectifier, but it shows the gate leakage current reduced to less than 1/4 and the power consumption reduced more than 30% at the load resistor, and it shows more stable DC supply voltages for the valiance of load resistance. In addition, the proposed rectifier shows high enough and well-rectified DC voltages for the frequency range of 13.56MHz HF(for ISO 18000-3), 915MHz UHF(for ISO 18000-6), and 2.45 GHz microwave(for ISO 18000-4). Therefore, the proposed rectifier can be used as a general purpose one to drive RFID transponder chips on various RFID systems which use specified frequencies.