• Title/Summary/Keyword: 초광대역 CMOS 저잡음증폭기

Search Result 2, Processing Time 0.015 seconds

Design of UWB CMOS Low Noise Amplifier Using Inductor Peaking Technique (인덕터 피킹기법을 이용한 초광대역 CMOS 저잡음 증폭기 설계)

  • Sung, Young-Kyu;Yoon, Kyung-Sik
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.17 no.1
    • /
    • pp.158-165
    • /
    • 2013
  • In this paper, a new circuit topology of an ultra-wideband (UWB) 3.1-10.6GHz CMOS low noise amplifier is presented. The proposed UWB low noise amplifier is designed utilizing RC feedback and LC filter networks which can provide good input impedance matching. In this design, the current-reused topology is adopted to reduce the power consumption and the inductor-peaking technique is applied for the purpose of bandwidth extension. The performance results of this UWB low noise amplifier simulated in $0.18-{\mu}m$ CMOS process technology exhibit a power gain of 14-14.9dB, an input matching of better than -10.8dB, gain flatness of 0.9dB, and a noise figure of 2.7-3.3dB in the frequency range of 3.1-10.6GHz. In addition, the input IP3 is -5dBm and the power consumption is 12.5mW.

Design of a CMOS LNA for MB-OFDM UWB Systems (MB-OFDM 방식의 UWB 시스템을 위한 CMOS LNA 설계)

  • Lee Jae-kyoung;Kang Ki-sub;Park Jong-tae;Yu Chong-gun
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.10 no.1
    • /
    • pp.117-122
    • /
    • 2006
  • A CMOS LNA based on a single-stage cascode configuration is designed for MB-OFDM ultra-wide band(UWB) systems. Wideband($3.1GHz\~4.9GHz$) input matching is performed using a simple bandpass filter to minimize the chip size and the noise figure degradation. The simulation results using $0.18{\mu}m$ CMOS process parameters show a power gain of 9.7dB, a 3dB band width of $2.1GHz\~7.1GHz$, a minimum NF of 2dB, an IIP3 of -2dBm. better than -11.8dB of input matching while occupying only $0.74mm^2$ of chip area. It consumes 25.8mW from a 1.8V supply.