• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.05a
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• pp.683-684
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• 2016

The up-to-date high-performance DSP or FPGA employs SRIO(Serial Rapid IO) as a high-speed serial communications. SRIO is an industry standard regulated upto Ver 3.1. In this study we developed a backplane having a transmission rate to 15Gbps based on a TI DSP. The back plane icould be used to High-speed video transmission, and will be adopted to connecting multiple DSPs for scalable architecture. This paper will discuss the design constraints for a high-speed communication and multiple-core operation.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.4 no.4
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• pp.323-328
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• 2003

In this paper new control strategy of series resonant converter system for power supply of communication station is suggested. Frequency controlled series resonant converter system is robust to load variations because it is POSR(Parallel Output Series Resonant: POSR) type. And it provides stable output voltage by changing switching frequency to input voltage variations. Firstly, operation analysis about suggested series resonant converter system was carried. Then simulations using ACSL(Advanced Continuous Simulation Langage) and experiments to actual system were carried to prove characteristics of suggested system.

• The Journal of the Convergence on Culture Technology
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• v.3 no.3
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• pp.27-30
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• 2017

IoT could be applied to various areas because of the important role of sensor. The existing sensor communication method is to quickly transmit data by using clock and two data pins based on the I2C serial communication method. As the objects used are gradually light-weighted and the amount of data transmission is decreased, the simplification of hardware is more emphasized as an essential design element than the speed of transmission. This paper designed a circuit to send/receive data in series, and also realized arduino, by analyzing the existing communication method and then using a single pin for light-weight. The single pin serial communication could reduce power consumption, which is suitable for the sensor area using digital communication of IoT area.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.4A
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• pp.519-527
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• 2000

This paper suggests and analyzes the Serially Concatenated Space-Time Code(SCSTC) with the possibility of a efficient high-speed transmission in a band limited channel. The suggested code has a structure that uses the interleaver to connect the space-time code as an inner code and the convolutional code as a outer code serially. This code keeps the advantage of high-speed transmission and also has the high BER performance. The performance of the suggested system is compared with the conventional bandwidth efficient trellis coded modulation, such as a Serially Concatenated Trellis Coded Modulation (SCTCM) and a Turbo-Trellis Coded Modulation(Turbo-TCM). The results show that the suggested system has a 2.8dB and 3dB better BER performance than SCTCM and Turbo-TCM respectively in case of the transmission rate 2b/s/Hz in fading channel.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.15 no.4
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• pp.230-236
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• 2022

In this paper, we propose an efficient concatenated code for both random and ISI errors on diffusion-based molecular communication channels. The proposed concatenated code was constructed by combining the ISI-mitigating code designed for ISI mitigation and the ISI-Hamming code strong against random errors, and the BER(bit error rate) performance was analyzed through simulation. In the case of the above M=1,200 channel environment, it was found that the error rate performance of the concatenated code follows the error rate performance of the ISI-mitigating code, which is strong against ISI, and follows the error rate performance of the ISI-Hamming code, which is strong against random errors, in the channel environment below M=600. In M=600~1,200, the concatenated code shows the best error rate performance among those of three codes, which is analyzed because it can correct both random errors and errors caused by ISI. In the following cases of below M=800, it can be seen that the error rate of the concatenated code and the ISI-mitigating code shows an error rate difference of about 1.0×10^-1 on average.

• Proceedings of the Korea Association of Information Systems Conference
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• 2002.11a
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• pp.283-288
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• 2002

본 연구에서는 소프트웨어를 원격 제어하기 위해 상용화된 적외선 수신부의 회로를 변경하여 컴퓨터의 직렬포트와 통신이 가능하도록 MAX232를 이용한 수신부를 개발하고, 컴퓨터에서 리모컨의 적외선 수신이 가능한 직렬통신 프로그램을 개발한다. 아울러 수신된 적외선신호를 일반 응용프로그램에서 적용이 가능한 형태로 신호를 변환한 다음 산업체 현장에서의 각종 응용소프트웨어에 적용 할 수 있도록 한다.

• Proceedings of the Korea Society for Industrial Systems Conference
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• 2004.06a
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• pp.135-139
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• 2004

본 연구에서는 소프트웨어를 원격제어 하기 위해 상용화된 적외선 수신부의 회로를 변경하여 컴퓨터의 직렬포트와 통신이 가능하도록 MAX232 ONE-CHIP 컴퓨터를 이용한 수신부를 개발하고, 컴퓨터에서 리모컨의 적외선 수신이 가능한 직렬통신 프로그램을 개발한다. 아울러 수신된 적외선 신호를 일반 응용 프로그램에서 적용이 가능한 형태로 신호를 변환한 다음 각종 응용 소프트웨어에 적용이 가능하도록 한다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.4C
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• pp.337-342
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• 2010

In this paper, a new architecture for digit-parallel/bit-serial GF($2^m$) multiplier with low complexity is proposed. The proposed multiplier operates in polynomial basis of GF($2^m$) and produces multiplication results at a rate of one per D clock cycles, where D is the selected digit size. The digit-parallel/bit-serial multiplier is faster than bit-serial ones but with lower area complexity than bit-parallel ones. The most significant feature of the digit-parallel/bit-serial architecture is that a trade-off between hardware complexity and delay time can be achieved. But the traditional digit-parallel/bit-serial multiplier needs extra hardware for high speed. In this paper a new low complexity efficient digit-parallel/bit-serial multiplier is presented.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2004.05b
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• pp.255-258
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• 2004

Efficient finite field operation in the elliptic curve (EC) public key cryptography algorithm, which attracts much of latest issues in the applications in information security, is very important. Traditional serial finite multipliers root from Mastrovito's serial multiplication architecture. In this paper, we adopt the polynomial basis and propose a new finite field multiplier, inducing numerical expressions which can be applied to exhibit 3 times as much performance as the Mastrovito's. We described the proposed multiplier with HDL to verify and evaluate as a proper hardware IP. HDL-implemented serial GF (Galois field) multiplier showed 3 times as fast speed as the traditional serial multiplier's adding only Partial-sum block in the hardware.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.9 no.1
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• pp.39-45
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• 2009

OFDM is used for achieving a high-speed data transmission in mobile wireless communication systems. Conventionally, fast Fourier transform that is the main signal processing of OFDM is implemented using digital signal processing. The DSP FFT LSI requires large power consumption. Current-mode FFT LSI with analog signal processing is one of the best solutions for high speed and low power consumption. However, for the operation of current-mode FFT LSI that has the structure of parallel-input and parallel-output, current-mode serial-to-parallel and parallel-to-serial converter are indispensable. We propose a novel current-mode SPC and PSC and full chip simulation results agree with experimental data. The proposed current-mode SPC and PSC promise the wide application of the current-mode analog signal processing in the field of low power wireless communication LSI.