• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.36-42
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• 2008

40Gb/s CMOS Clock and Data Recovery circuit design for optical serial link is proposed. The circuit generates 8 multiphase clock using LC tank PLL and controls the phase between the clock and the data using the $2{\times}$ oversampling Bang-Bang PD. 40Gb/s input data is 1:4 demultiplexed and recovered to 4 channel 10Gb/s outputs. The design was progressed to separate the analog power and the digital power. The area of the chip is $2.8{\times}2.4mm^2$ for the inductors and the power dissipation is about 200mW. The chip has been fabricated using 0.18um CMOS process. The measured results show that the chip recovers the data up to 9.5Gb/s per channel(Equivalent to serial input rate of up to 38Gb/s).

• Annual Conference on Human and Language Technology
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• 1999.10d
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• pp.60-75
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• 1999

품사 태깅은 자연 언어 처리의 가장 기본이 되는 부분으로 상위 자연 언어 처리 부분인 구문 분석, 의미 분석의 전처리로 사용되고, 독립된 응용으로 언어의 정보를 추출하거나 정보 검색 등의 응용에 사용되어 진다. 품사 태깅은 크게 통계에 기반한 방법, 규칙에 기반한 방법, 이 둘을 모두 이용하는 혼합형 방법 등으로 나누어 연구되고 있다. 포항공대 자연언어처리 연구실의 자연 언어 처리 엔진(SKOPE)의 품사 태깅 시스템 POSTAG는 미등록어 추정이 강화된 혼합형 품사 태깅 시스템이다 본 시스템은 형태소 분석기, 통계적 품사 태거, 에러 수정 규칙 후처리기로 구성되어 있다. 이들은 각각 단순히 직렬 연결되어 있는 것이 아니라 형태소 접속 테이블을 기준으로 분석 과정에서 형태소 접속 그래프를 생성하고 처리하면서 상호 밀접한 연관을 가진다. 그리고, 미등록어용 패턴사전에 의해 등록어와 동일한 방법으로 미등록어를 처리함으로써 효율적이고 강건한 품사 태깅을 한다. 한편, POSTAG에서 사용되는 태그세트와 한국전자통신연구원(ETRI)의 표준 태그세트 간에 양방향으로 태그세트 매핑을 함으로써, 표준 태그세트로 태깅된 코퍼스로부터 POSTAC를 위한 대용량 학습자료를 얻고 POSTAG에서 두 가지 태그세트로 품사 태깅 결과 출력이 가능하다. 본 시스템은 MATEC '99'에서 제공된 30000어절에 대하여 표준 태그세트로 출력한 결과 95%의 형태소단위 정확률을 보였으며, 태그세트 매핑을 제외한 POSTAG의 품사 태깅 결과 97%의 정확률을 보였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.68-75
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• 2007

A single chip NFC transceiver supporting not only NFC active and passive mode but also 13.56MHz RFID reader and tag mode was designed and fabricated. The proposed NFC transceiver can operate as a RFID tag even without external power supply which has dual antenna structure for initiator and target. The area increment due to additional target antenna is negligible because the target antenna is constructed by using a shielding layer of initiator antenna. The analog front end circuit of the proposed NFC transceiver consists of a transmitter and receiver of reader/writer block supporting NFC initiator or RFID reader mode, and a tag circuit for target of passive NFC mode or RFID tag mode. The maximum baud rate of the proposed NFC device is 212kbps by using UART serial interface. The chip has been designed and fabricated using a Magnachip's $0.35{\mu}m$ double poly 4-metal CMOS process, and the effective area of the chip is 2200um by 3600um.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.10
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• pp.70-78
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• 2009

This paper addresses the analysis and the design optimization of differential interconnects for high-speed Low-Voltage Differential Signaling (LVDS) applications. Thanks to the differential transmission and the low voltage swing, LVDS offers high data rates and improved noise immunity with significantly reduced power consumption in data communications, high-resolution display, and flat panel display. We present an improved model and new equations to reduce impedance mismatch and signal degradation in cascaded interconnects using optimization of interconnect design parameters such as trace width, trace height and trace space in differential printed circuit board (FPCB) transmission lines. We have carried out frequency-domain full-wave electromagnetic simulations, and time-domain transient simulations to evaluate the high-frequency characteristics of the differential FPCB interconnects. We believe that the proposed approach is very helpful to optimize high-speed differential FPCB interconnects for LVDS applications.

• Journal of KIISE:Computing Practices and Letters
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• v.5 no.4
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• pp.479-488
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• 1999

인터넷의 성장과 더불어 수많은 응용시스템들이 인터넷 기반 시스템으로 바뀌고 있다. 특히, 인터넷 기반 전문가시스템은 다양한 구조와 방법으로 설계될 수 있고 이미 제작되었던 수많은 인터넷 기반 전문가시스템들은 그 나름대로의 장단점을 가지고 있다. 본 연구는 특정 전문가시스템의 개발이 아니라 WWW(World Wide Web)을 사용자 인터페이스로 이용할 수 있는 전문가시스템 쉘에 관한 연구이다. 본 시스템은 WWW 하부구조에 대한 의존성을 제거, 클라이언트와 네크워크에 부담 격감, HTML과 부합하는 텍스트에 기초한 통신과 같은 장점 외에 중앙 집중적 다중 사용자 접근 관리 기능을 제공한다. 본 시스템은 다중사용자를 위한 서버/클라이언트 환경 구축을 위해 소켓을 이용하여 큐잉(queueing)과 직렬화(serialization)를 해결하고 비연결 지향적인 WWW의 특성으로 인한 사용자 관리의 어려움은 사용자의 IP 주소와 Timer를 이용한 휴무기간 검사를 이용하여 해결한다.Abstract The growth of internet drives many applications into internet-based systems. Internet-based expert systems can be designed with various concepts and methodologies, and they have their own merits and demerits. This papers is a study on a development of not expert system itself but expert system shell which is able to use WWW(World Wide Web) as user interface. The suggested system supports functions on multiuser management controlled by a server system as well as independence on development environments, minimization of the load for clients and network, and text-based communications such as HTML. The system uses socket, which solves problems of queuing and serialization, in order to construct multiuser server/client environmen and also the system solves the non-connective property of WWW which makes it difficult to control users and processes by using IP address and idle time which is supported by the timer.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.20 no.10
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• pp.126-134
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• 2006

This paper describes the development of an embedded wireless LAN controller which can be in parallel operated with an existing utility controller. The embedded controller mainly consists of Prism(R) 2.5 chip set and Atmega 128 microcontroller. In order to communicate over the network, the controller including TCP/IP stack (IP, TCP, UDP, and ICMP), telnet, and X/Z modem has been developed. For a specific application, we have proposed an special method to convert data structure between TCP/IP and X/Z modem and a data buffer algorithm to minimize the RAM memory usage. Finally, the correctness and performance of the protocols are tested and verified using $CommView^{(R)}\;and\;DU^{(R)}$. The development is satisfactorily operated only for 3,381 bytes of RAM usage without sacrificing interoperability between hosts.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.3
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• pp.401-408
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• 2001

This paper shows the design, fabrication and performance analysis of VCO which plays a major role in 5.8 GHz RF module for ITS. The design specifications of the VCO are determined on the basis of 5.8 GHz RF modul performance requirements. The design parameters are optimized through ADS simulation tool. The operating characteristic and performance analysis of the implemented VCO based on the design parameters are accomplished. The frequency variations according to the voltage change(0 ~5 V) of varactor diode are from 5.42 GHz to 5.518 GHz and the power level is 6.5 dBm. The second harmonic suppression are -21.5 dBc at 5.51 GHz and the phase noise characteristics are -83.81 dBc at 10 kHz offset frequency. The implemented VCO is available to not only DSRC and also, 5.8 GHz other systems.

• Journal of the Korean Institute of Intelligent Systems
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• v.19 no.5
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• pp.674-682
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• 2009

The modular robot is one which was developed to get over limit of the space movement for the mobile robot. The chain type robot in particular is connected by series each other and this form expression method is simple and easy to really make a docking method efficiently. However, the related studies were focused on the movement that used to be combination, and the movement of a cell independent mainly does not consist and have a problem to dock only in a direction, not to be connected with all directions. Therefore, we suggested a modular structure for quick, independent movement to solve such a problem and had own autonomy. In addition, we are intended to get some effectiveness for connection mechanism using one locking motor. In this paper, we dealt with the design for the mechanical and electrical points and docking algorithm including communication method. All of the structure is verified with real action experiment through the shape expressions of various application platform.

• Convergence Security Journal
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• v.21 no.2
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• pp.29-35
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• 2021

UART (Universal asynchronous receiver/transmitter) is a hardware device that converts data into serial format and transmits it, and is widely used for system diagnosis and debugging in most embedded systems. Hackers can access system memory or firmware by using the functions of UART, and can take over the system by acquiring administrator rights of the system. In this paper, we studied secure UART to protect against hacker attacks through UART. In the proposed scheme, only authorized users using the promised UART communication protocol are allowed to access UART and unauthorized access is not allowed. In addition, data is encrypted and transmitted to prevent protocol analysis through sniffing. The proposed UART technique was implemented in an embedded Linux system and performance evaluation was performed.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.13 no.4
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• pp.139-149
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• 2003

In this paper a hardware design of area-efficient hash processor which implements MD5 algorithm using hardware sharing and carry-save addition schemes is described. To reduce area, the processor adopts hardware sharing scheme in which 1 step operation is divided into 2 substeps and then each substep is executed using the same hardware. Also to increase clock frequency, three serial additions of substep operation are transformed into two carry-save additions and one carry propagation addition. The MD5 hash processor is designed using 0.25 $\mu\textrm{m}$CMOS technology and consists of about 13,000 gates. From timing simulation results, the designed MD5 hash processor has 465 Mbps hash rates for 512-bit input message data under 120 MHz operating frequency.