• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.4
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• pp.891-896
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• 2011

This paper describes the differential voltage-to-frequency converter which is realized current conveyor circuits. The output frequency of the differential voltage-to-frequency converter is proportional to the difference of two input voltages. The designed circuit is simulated by HSPICE. The range of input voltage difference is from several volts to several milli-volts. From the simulation results the error is less than from -1.9% to +1.8% compared to the calculated values.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.6
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• pp.63-70
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• 2014

A low-N phase-locked loop clock generator with frequency multiplier is proposed to improve phase noise characteristic. Delay-variance voltage converter (DVVC) generates output voltages according to the delay variance of delay stages in voltage controlled oscillator. The output voltages of average circuit with the output voltages of DVVC are applied to the delay stages in VCO to reduce jitter. The HSPICE simulation of the proposed phase-locked loop clock generator with a $0.18{\mu}m$ CMOS process shows an 11.3 ps of peak-to-peak jitter.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.14 no.1
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• pp.37-42
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• 2021

This paper presents a jitter and phase noise characteristic improved phase-locked loop (PLL) with loop filter voltage detector(LFVD) and frequency voltage converter(FVC). Loop filter output voltage variation is determined through a circuit made of resistor and capacitor. The output signal of a small RC time constant circuit is almost the same as to loop filter output voltage. The output signal of a large RC time constant circuit is the average value of loop filter output voltage and becomes a reference voltage to the added LFVD. The LFVD output controls the current magnitude of sub-charge pump. When the loop filter output voltage increases, LFVD decreases the loop filter output voltage. When the loop filter output voltage decreases, LFVD increases the loop filter output voltage. In addition, FVC also improves the phase noise characteristic by reducing the loop filter output voltage variation. The proposed PLL with LFVD and FVC is designed in a 0.18um CMOS process with 1.8V power voltage. Simulation results show 0.854ps jitter and 30㎲ locking time.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.12
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• pp.2933-2938
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• 2014

In this paper, the FLL(Frequency Locked Loop) circuit using current conveyor circuit is designed by $0.35{\mu}m$ CMOS process. The FLL circuit is built in a frequency divider, a frequency-to-voltage converter, a voltage subtractor and a oscillator and the circuit blocks have a symmetric structure to improve a reliability characteristics with a process variation. From the simulation results, the variation rate of output frequency is about less than ${\pm}1%$ when the channel length, channel width, resistance and capacitance are varied ${\pm}5%$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.5
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• pp.1119-1124
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• 2011

The operation of current conveyor circuit is similar to an operational amplifier and a current conveyor circuit has the characteristics such as good linearity and stability. In this paper, a frequency-to-voltage converter circuit is designed by using a current conveyor circuit. The supply voltage is 5volts and the designed circuit is simulated by HSPICE. The range of the input frequency is from 4kHz to 200kHz. From the simulation results the error of the output voltages is less than from -1.3% to +2.5% compared to the calculated values.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.7B
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• pp.891-894
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• 2001

본 논문에서는 능동 배열 안테나에서 RF 대신 중간주파수를 이용하여 빔 추적을 하는 방법이 연구되었다. 안테나의 각 배열은 전압제어 발진기, 위상추적기, 혼합기와 결합되어 있으며 혼합기는 안테나 상에서 직접 RF 신호를 직접 중간주파수 신호로 변환시킨다. 전압제어 발진기 입력은 위상추적기에 의하여 조절되며 배열 안테나의 주사범위는 위상추적기와 전압제어발진기에 의하여 결정되었다.

• Proceedings of the KIEE Conference
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• 2015.07a
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• pp.1064-1065
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• 2015

단상 계통 연계형 전력 변환기에서 계통과 연계하기 위해서는 계통의 위상 정보를 정확히 측정하여 전력 변환기의 출력 주파수와 위상이 동일한 상태로 전류가 공급 되도록 해야 한다. 본 논문에서는 단상 d-q 좌표 변환 기법을 통한 위상 동기화 기법을 적용하여 왜곡된 계통전압이 d축 전압에 야기 되는 에러 성분을 최소화 하는 보상 기법을 제안한다. 제안된 기법은 동기 d축 전압을 일정한 주기로 적분하여 에러 성분을 최소화 한 후, PI제어를 통해 d축 전압을 0으로 수렴하게 하는 기법이다. 제안된 기법은 추가적인 하드웨어를 요구하지 않는다. 본 논문의 타당성을 검증하기 위해 3[kW]급 단상 계통 연계형 전력변환기 시작품을 제작하고 실험을 통해 증명하였다.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.1
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• pp.139-144
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• 2016

This paper describes functional circuits of DC-DC converter IC incorporated with variable frequency PFM technique. In case of output voltage of DC-DC converter is reached setting value or output current is low then PFM switching frequency is slow down. In this work a PFM signal generator, a PFM Frequency Control Circuit, an output voltage detector and an over current protection circuits are designed. This device has been designed at a $0.35[{\mu}m]$, double poly, double metal 12[V] CMOS process.

• 전기의세계
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• v.45 no.7
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• pp.39-44
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• 1996

전력변환 시스템의 고성능화를 위해서는 스윗칭 주파수를 고주파수로 하는 것이 필요하다. 그러나 PWM방식에서는 반도체 소자를 강제적으로 스윗칭시키기 때문에 고주파 스윗칭을 행하면 EMI, EMC 문제를 무시할 수 없게 되고 스윗칭 손실은 스윗칭 주파수와 함께 증가한다. 이 문제를 해결하기 위해 1986년에 미국 위스콘신대학에서 당초 인공위성 등에 탑재하는 직류전원으로서 직류/직류 컨버터의 공진 스위치였던 회로구성을 3상 직류링크 전압형 인버터에 전개하여 소프트 스윗칭이 가능하게 되는 교류전원용의 전압형 인버터를 발표하였다. 또한 그 당시에 또 다른 공진형 회로구성인 교류링크 인버터도 발표되었다[3-5]. 이러한 배경으로 이하에서는 PWM 전력변환기의 소개를 시작으로 고주파수화의 필요성 및 그로 인해 파생되는 문제점을 고찰하고, 공진형 전력변환 시스템의 필요성에 대하여 논한 뒤 각종의 공진형 변환기에 대하여 간략하게 설명하고자 한다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.42 no.4
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• pp.864-870
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• 2017

This paper describes a Dual Buck Converter with mode control using variable Frequency to Voltage for portable devices requiring wide load current. The inherent problems of PLL compensation and efficiency degradation in light load current that the conventional hysteretic buck converter has faced have been resolved by using the proposed Dual buck converter which include improved PFM Mode not to require compensation. The proposed mode controller can also improve the difficulty of detecting the load change of the mode controller, which is the main circuit of the conventional dual mode buck converter, and the slow mode switching speed. the proposed mode controller has mode switching time of at least 1.5us. The proposed DC-DC buck converter was implemented by using $0.18{\mu}m$ CMOS process and die size was $1.38mm{\times}1.37mm$. The post simulation results with inductor and capacitor including parasitic elements showed that the proposed circuit received the input of 2.7~3.3V and generated output of 1.2V with the output ripple voltage had the PFM mode of 65mV and 16mV at the fixed switching frequency of 2MHz in hysteretic mode under load currents of 1~500mA. The maximum efficiency of the proposed dual-mode buck converter is 95% at 80mA and is more than 85% efficient under load currents of 1~500mA.