• Science of Emotion and Sensibility
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• v.13 no.4
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• pp.703-710
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• 2010

In this study, a tactile stimulator was developed to resolve some problems from the previous version of the system such as system configuration, inappropriate stimulation control and additional problems. The developed tactile stimulator consists of control unit, drive unit and vibrator unit. The control unit was controlled by E-Prime software to generate appropriate vibration pulses. The drive unit supplies enough energy to the vibrator to generate effective stimulation pulses. The vibrator unit consists of small coin type vibrator and velcro, and was made to be attached at the hand easily. The developed tactile stimulator was designed by small-size, light-weight, low-power, simple-fabrication, max 35 channels and little delay time from instruction signal of E-Prime software to vibrator. The duration and magnitude of stimulation was controlled by 10 grades and the problems concerning stimulation control were compensated by wideband frequency ranges. Additionally, the electrical safety was ensured by low voltage operation. Vibrator was made to be attached on finger as well as on any part of the subject. Since this tactile stimulator is developed based on E-Prime software which is widely used in cognitive science, it is believed that this stimulator be suitable for the wide application of cognitive science study.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.9
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• pp.63-73
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• 2015

This work proposes a 2-channel time-interleaved (T-I) 10b 120MS/s pipeline SAR ADC minimizing offset mismatch between channels without any calibration scheme. The proposed ADC employs a 2-channel SAR and T-I topology based on a 2-step pipeline ADC with 4b and 7b in the first and second stage for high conversion rate and low power consumption. Analog circuits such as comparator and residue amplifier are shared between channels to minimize power consumption, chip area, and offset mismatch which limits the ADC linearity in the conventional T-I architecture, without any calibration scheme. The TSPC D flip-flop with a short propagation delay and a small number of transistors is used in the SAR logic instead of the conventional static D flip-flop to achieve high-speed SAR operation as well as low power consumption and chip area. Three separate reference voltage drivers for 4b SAR, 7b SAR circuits and a single residue amplifier prevent undesirable disturbance among the reference voltages due to each different switching operation and minimize gain mismatch between channels. High-frequency clocks with a controllable duty cycle are generated on chip to eliminate the need of external complicated high-frequency clocks for SAR operation. The prototype ADC in a 45nm CMOS technology demonstrates a measured DNL and INL within 0.69LSB and 0.77LSB, with a maximum SNDR and SFDR of 50.9dB and 59.7dB at 120MS/s, respectively. The proposed ADC occupies an active die area of 0.36mm2 and consumes 8.8mW at a 1.1V supply voltage.