• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.14 no.10
• /
• pp.5134-5139
• /
• 2013

Ladder Diagram(LD) or Sequential Function Chart(SFC) is used for the design of complex modern control system with Programmable logic controller(PLC). LD is the most widely utilized among PLC standard language. But recently, SFC is used frequently. SFC is very easy to grasp the sequential flow of control logic but is difficult for describing combinational logic. When the interrupt factor is occurred, the main program is stopped. And after the interrupt program is completed, the main program is restart. Therefore the more complex the interrupt program, the main program is interrupted downtime will be that much longer. In this paper, we propose the method for interrupt implementation without the dwell time of the main program by SFC language and confirm his feasibility through the simulation.

• Electronics and Telecommunications Trends
• /
• v.3 no.2
• /
• pp.116-133
• /
• 1988

ASIC (Application Specific Integrated Circuit)은 직역하면 응용특정 IC, 혹은 특정용도 IC로서 LSI시장의 조사회사인 Dataquest사가 '84년경부터 사용하기 시작한 말이다. ASIC이 최근 크게 주목을 끌고있는 것은, 반도체 사용자가 자신의 제품에 개성을 불어넣기 위해서는 범용IC를 사용해온 것으로는 기술적 우위성이 확보되지 않는다고 판단했기 때문에 주문형 LSI를 강하게 추진해 왔다는 것과 반도체 메이커도 메모리IC를 중심으로 한 범용IC시장의 부진, 더우기 날로 더해가는 반도체 시장의 시장쟁탈 및 무역마찰로 인해 ASIC 시장에로의 참여가 강화되어 왔다는 점 등을 들수있다. 집적화 기술은 매년 진보하여 지금은 100만개 이상의 트랜지스터를 집적할 수 있게 되었다. 따라서 지금까지 SSI/MSI를 사용해서 회로설계한 기능단위의 칩을 프린터 기판위에 조합시켜 시스팀을 구축해 왔으나, 앞으로는 하나의 칩위에 시스팀을 구성하는 시대로 변하고 있다. ASIC은 그 요청에 따라서 one-chip화의 개념에 따라서 만들어진 것으로서, 시장환경에 대단히 유익한 디바이스로 생각할 수 있다. 시스팀의 one-chip화의 실현결과 압도적으로 소형화, 경량화, 성자원화가 달성됨과 동시에 신뢰성 및 동작성능도 우수하게 되었다. ASIC기술은 현재 주류로 되어있는 게이트 어레이를 볼때, 개발비용은 크게 감소하여 개발기간도 논리회로가 완성된다면 3~4주 정도로 단축시킬수 있다. ASIC 설계에는 각 공정에 있어서 고도의 컴퓨터 지원설계가 채용되고 제조공정에서는 첨단의 프로세서 기술 등이 이용되므로 ASIC기술은 종합적인 첨단기술의 집약이라고 불러도 좋을것이다. 이러한 기술추세에 맞추어 전자통신 동향분석지 제3권 제1호(1988.3.)에 발표된 최신 ASIC기술동향의 후속편으로 ASIC에 관련된 중요용어 50개를 선정, 알파벳 순으로 나열하여 설명하였다.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2021.11a
• /
• pp.819-822
• /
• 2021

AI World Cup 환경은 다수 가상 에이전트들이 팀을 이뤄서 서로 상호작용하며 대전이 가능한 가상 축구 환경이다. 본 논문에서는 AI World Cup 환경에서 멀티 에이전트기반 학습/추론 기술을 사용하여 다양한 전략과 전술을 구사하는 가상 축구 에이전트 구현과 시뮬레이션 결과를 소개한다. 먼저, 역할을 바탕으로 협동하여 상대방과 대전할 수 있는 논리 기반 추론형 멀티 에이전트 기술이 적용된 Dynamic planning 축구 에이전트 9 세트를 구현하였다. 이후, 강화학습 에이전트 기반, 단일 에이전트를 조합한 Independent Q-Learning 방식의 학습형 축구 에이전트를 구현한 후, 이를 멀티 에이전트 강화학습으로 확장하여 역할 기반 전략 학습이 가능한 가상 축구 에이전트를 구현하고 시뮬레이션 하였다. 구현된 가상 축구 에이전트들 간 대전을 통해 승률을 확인하고, 전략의 우수성을 분석하였다. 시뮬레이션 예제는 다음에서 확인할 수 있다 (https://github.com/I-hate-Soccer/Simulation).

• Journal of Venture Innovation
• /
• v.3 no.2
• /
• pp.95-109
• /
• 2020

The source of value-added creation in modern times has been transformed from material to man's value-added generating power, and ownership of the means of production has been converted from a particular landlord, capitalist to a person with value-added capacity, and a system of capital participation is needed beyond the profit-sharing system or performance incentive system in which workers of an enterprise participate in simple profits if they significantly increase the added value of the company. It is also necessary to introduce our private stock system as a means of addressing the problem of capital bias and for the stable development of capitalism. The purpose of Employee Stock Ownership Plans is to improve the economic and social status of workers and promote labor-management cooperation by allowing workers to acquire and hold shares of the stock company in which the employee ownership association is established through the employee ownership association, but the reality is that our stock ownership system has failed to achieve its purpose due to insufficient protection against the employee. In terms of welfare, the acquisition of our company shares should include active government support for the welfare of workers' ownership on a social welfare level rather than on the logic of the capital market, and in terms of investment, it would not be appropriate to apply the regulation for investor protection to see workers' acquisition of our company shares as 'investment' in the view of workers' willingness to own shares on the stock market. Therefore, as a way to support and deregulate employee's stock acquisition, 1. Expanding direct support, such as tax support, 2. As employee's stock ownership association is being discussed as a division's nature, it is less effective in terms of various management, not investment, and 3. Those who own stocks with 1% of the company's shares and 300 million won in face value will be classified as major shareholders. As a way to reduce the risk of management of our company owners and cooperative funds, As a measure to reduce the risk of management of our company owners and cooperative funds, only our employee shareholders' association shall manage the fund in a long-term deposit, and even though our employee's stock is managed by the association or company after the end of the deposit period, the management of each employee shall be allowed and In terms of improving the utilization of our company's stock and fund, 1. Employee's stockholders are prohibited from lending during the deposit period, but it is necessary to improve profitability by allowing them to borrow under strict restrictions, 2. It is necessary to make the use of the employee's welfare funds available for the preservation of losses, and to stipulate the redemption obligations of unlisted companies in order to improve the redemption system of our company.

• 대한공업교육학회지
• /
• v.33 no.1
• /
• pp.149-168
• /
• 2008

The purpose of this study is to verify the effect of PSpice instruction on academic achievement in 'Combination logic circuit' unit of 'Digital Logic Circuit' in industrial high school. Three kinds of null hypotheses were formulated. Two classes of the third grade of C technical high school in Gyeong-buk were divided into experimental group and control group in order to verify null hypotheses. In the experimental design, 'Non-equivalent control group pretest-posttest' model was utilized. This experiment was conducted for six classes, the experimental group was applied to PSpice instruction method before the circuit traning while the control group was applied to traditional lecture oriented method before the circuit traning. Window SPSS 10.0 korean language version program was used for the data analysis and independent sample t-test was used to identify the average of each group. Significance level was set to .05 level. The results obtained in this study were as follows; First, PSpice instruction had not an effect on academic achievement according to a group type. However, these instruction had an effect on the following sub-domains; the psychomotor domain. Second, PSpice instruction had not an effect on academic achievement according to a studies level. However, these instruction for middle and low level students had an effect on the cognitive and psychomotor domain, and for middle level students had an effect on the affective domain. Third, PSpice instruction had not an effect on shortening of a training requirement. However, this instruction for low level students had an effect on shortening of a training requirement. The study results of simulation instruction was chiefly efficient in the psychomotor domain. We could know that simulation instruction is efficient as went to a low level students than an upper level students. Thus, We may make the study effectiveness in various instruction method.

• Journal of the Korean Institute of Telematics and Electronics T
• /
• v.36T no.4
• /
• pp.71-81
• /
• 1999

We propose a new CPLD(Complexity Programmable Logic Device) technology mapping algorithm improving run-time under time constraint. In our technology mapping algorithm, a given logic equation is constructed as the DAG(Directed Acyclic Graph) type, then the DAG is reconstructed by replicating the node that outdegree is more than or equal to 2. As a result, it makes delay time and the number of CLBs, run-time to be minimized. Also, after the number of multi-level is defined and cost of each nodes is calculated, the graph is partitioned in order to fit to k that is the number of OR term within CLB. The partitioned nodes are merged through collapsing and bin packing is performed in order to fit to the number of OR term within CLB(Configurable Logic Block). In the results of experiments to MCNC circuits for logic synthesis benchmark, we can shows that proposed technology mapping algorithm reduces run-time and the number of CLBs much more than the TEMPLA.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.37 no.4
• /
• pp.80-89
• /
• 2000

In this paper, we propose a new CPLD technology mapping algorithm for sequential circuit under time constraints. The algorithm detects feedbacks of sequential circuit, separate each feedback variables into immediate input variable, and represent combinational part into DAG. Also, among the nodes of the DAG, the nodes that the number of outdegree is more than or equal to 2 is not separated, but replicated from the DAG, and reconstructed to fanout-free-tree. To use this construction method is for reason that area is less consumed than the TEMPLA algorithm to implement circuits, and process time is improved rather than TMCPLD within given time constraint. Using time constraint and delay of device the number of partitionable multi-level is defined, the number of OR terms that the initial costs of each nodes is set to and total costs that the$^1$costs is set to after merging nodes is calculated, and the nodes that the number of OR terms of CLBs that construct CPLD is excessed is partitioned and is reconstructed as subgraphs. The nodes in the partitioned subgraphs is merged through collapsing, and the collapsed equations is performed by bin packing so that it fit to the number of OR terms in the CLBs of a given device. In the results of experiments to MCNC circuits for logic synthesis benchmark, we can shows that proposed technology mapping algorithm reduces the number of CLBs by 15.58% rather than the TEMPLA, and reduces process time rather than the TMCPLD.

• The Transactions of the Korea Information Processing Society
• /
• v.7 no.1
• /
• pp.224-234
• /
• 2000

In this paper, we propose a new CPLD technology mapping algorithm for sequential circuit under time constraints. The algorithm detects feedbacks of sequential circuit, separate each feedback variables into immediate input variable, and represent combinational part into DAG. Also, among the nodes of the DAG, the nodes that the number of outdegree is more than or equal to 2 is not separated, but replicated from the DAG, and reconstructed to fanout-free-tree. To use this construction method is for reason that area is less consumed than the TEMPLA algorithm to implement circuits, and process time is improved rather than TMCPLD within given time constraint. Using time constraint and delay of device the number of partitionable multi-level is defined, the number of OR terms that the initial costs of each nodes is set to and total costs that the costs is set to after merging nodes is calculated, and the nodes that the number of OR terms of CLBs that construct CPLD is excessed is partitioned and is reconstructed as subgraphs. The nodes in the partitioned subgraphs is merged through collapsing, and the collapsed equations is performed by bin packing so that if fit to the number of OR terms in the CLBs of a given device. In the results of experiments to MCNC circuits for logic synthesis benchmark, we can shows that proposed technology mapping algorithm reduces the number of CLBs bu 15.58% rather than the TEMPLA, and reduces process time rather than the TMCPLD.

• Journal of the HCI Society of Korea
• /
• v.5 no.2
• /
• pp.7-14
• /
• 2010

Urban Data collected through Sensor Network is becoming crucial to understand and analyse a city. Thus, the Ubiquitous Sensor Network builds the foundation of the u-City development. This research aims to develop an energy monitoring application with an intuitive visualization environment which integrates energy usage information on top of urban geospatial information. Such a system will be able to facilitate effective energy supply plan at the early stages of urban planning, and eventually to encourage citizens to conserve energy by giving them real time monitoring information in an easy to understand visual environment. The system provides multiple layers of energy-related information coupled with the geospatial information layer in order to accommodate multiple viewpoints. On the other hand, the system provides logical Level of Detail control based on urban spatial information hierarchy. We defined the system concept and functions, and designed the data structure and the methods of information visualization. This paper presents the visualization methods, data structure, interactions scenarios which combines spacial information, E-GIS data and the energy related sensor data. Furthermore this research tries to introduce the concept of Social Sensor Networking to enhance the monitoring quality.

• Journal of the Korean Society of Costume
• /
• v.52 no.1
• /
• pp.53-67
• /
• 2002

자연을 분석함으로써, 얻어진 기하학적 패턴은 이미 자연의 질서를 포함하고 있는 논리적이고 합리적인 기본형이기 때문에 간결하며 시각적으로 명쾌감을 준다. 이러한 기하학적 패턴은 복식 디자인에 있어서 20 세기 이후 여러 디자이너의 작품을 통해 재구성되어 현대적 이미지를 나타내는 중요한 모티브가 되고 있으며, 다양한 기법과 재료로 형성화하여 도입되고 있다. 이에 본 연구는 복식의 문양, 실루엣, 디테일에 사용되고 있는 기하학적 패턴을 연구함으로써 기하학적 패턴의 새로운 조형가치를 고찰하였다. 먼저 기하학의 용어 정의를 하였고 기하학적 패턴의 유형과 표현 기법을 분석하고 정리하여 현대 패션에 나타난 기하학적 패턴의 조형미와 그것을 바탕으로 패션 이미지를 추론해 보았다. 현대 패션에 나타난 기하학 패턴을 분석해 보면 유형으로는 첫째, 기하하적 문양으로 복식디자인에 있어서 주로 평면적인 형태로 많이 나타나지만, 크기가 다르고 동일한 기하학적 패턴을 조합시킴으로서 평면적인 형태에 공간감을 부여하기도 하며, 같은 기하학적 패턴의 표면이라도 배치구조에 의해 직선 혹은 사선으로 지각되므로 전혀 다른 이미지를 주었다. 또한 현대 패션에 나타난 기하학적 패턴이 종류는 세로 스트라이프, 가로 스트라이프, 격자 문양, 원, 사선 스트라이프, 마름모, 사각형, 삼각형 등의 순서로 많이 나타났다. 둘째, 색채는 단색의 복식에 강한 대비가 이루어지는 색상으로 표현되어 역동감과 유연한 운동감을 나타났다. 셋째, 기하학적 실루엣으로 단순한 라인의 형태를 나타내거나 입체적이고 부조적인 형태로 구성되어 전체적인 실루엣으로 사용되어 강한 조형감각을 보여주는데 원형을 이용한 실루엣이 가장 많았으며 사각형을 이용한 실루엣, 삼각형을 이용한 실루엣 순서로 나타났다. 넷째, 기하학적인 디테일로 복식의 어느 한 부분에 장식적으로 사용되거나 입체적 형태로 부출 되어 부조적인 느낌을 주는데 소매에 가장 많이 나타났으며 앞여밈, 칼라, 밑단, 주머니 순서로 장식되었다. 다섯째, 현대 패션에 표현된 기하학적 패턴의 표현기법으로는 프린팅, 퀼팅, piece기법, 패치워크, 엮기, 꼴라쥬, 아플리케 순서로 많이 나타났다. 위의 분석을 토대로 기하학 패턴을 활용한 디자인에 내재된 조형의지는 다음과 같이 정리되었다. 첫째, 기하학적 패턴이 지닌 단순성과 경직성을 완화하기 위하여 여러 가지 패브릭을 조합시켜 입체적인 표면효과로 시각적인 착시효과를 극대화하였다. 둘째, 표현기법은 입체파적 표현주의의 특성의 하나로 복시에 사용되는 소재의 왜곡으로 설명할 수 있으며, 새롭고 실험적인 소재의 도입으로 인해 의외성과 부조화를 유발시키는 통시에 유희직인 일면도 지니는 일종의 그로테스크를 나타냈다. 이상에서 정립된 조형의지를 바탕으로 현대 패션에 나타란 기하학 패턴은 절제된 단순함과 명확성으로 단순미가 유추되었고 강한 색상대비로 인한 시각적 집중효과로 주목성을 가지며 재현이 가능하므로 반복성이 유추되었다. 그리고 표준영역이 없는 창의적 표현으로 풍부한 독창성을 보여주고 있다. 또한 내재된 패션 이미지를 분석해 보면 정확함과 차가움의 의미를 지닌 이지적 이미지와 우주의 질서를 반영하는 상징적 이미지, 복잡한 자연으로부터 간결한 형태로의 경향성이 이루어낸 인공적 이미지를 느낄 수 있었으며, 미래적 이미지와 전통적 이미지의 상반된 개념의 이미지를 같이 내포하고 있음을 추론할 수 있었다. 이와 같이 현대 패션에 표현된 기하학적 패턴은 복식을 조형예술 분야로 확실히 인식시키고 발전시키는 데 중요한 촉매제 역할을 담당하고 있으며 또한 많은 디자이너들에게 창조적 욕구를 불러일으키고 영감을 주는데 중요한 모티브를 제공하고 있다.