• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.12
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• pp.131-138
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• 2016

In this study, we tried to analyze the influence of ICM(Iodinated Contrast Media) in MR imaging compare to GBCA(Gadolinium Based Contrast Agent), and as this result we discussed whether resonable or not the protocol which is MRI scan after enhanced CT scan without proper time interval in clinical field. For this research, we assembled two phantoms. which one was iodine and another one was gadolinium. We did test two phantoms in conventional MRI scan which is T1, T2, T2 FLAIR and 3D angio. After that, quantitative analysis was progressed. The results of study were as follow : SSI(Saline's Signal Intensity) was shown as each sequences 175, 1231, 333, 37 [a.u] at iodine. and 1297, 123, 757, 232 [a.u] was recorded at gadolinium. BDEPS(the Biggest Difference of EPS) was shown as each sequences 1297, 123, 757, 232 [a.u] at iodine and 793, 6, 1495, 365 [a.u] was recorded at gadolinium. At this time, EPS(Enhancement Percentage to Saline) was shown 641.1, -90.0, 127.3, 527% at iodine and 685.1, 99.4, 365.7, 1077.4% was recorded at gadolinium. BP(BDEPS's point) was shown 900, 900, 477, 900 mmol at iodine and 4, 0.2, 0.2, 40 mmol was recorded at gadolinium. CPSS(Change Point of SI to SSI) was shown 63, 423, 63, 29 mmol at iodine and each [50, 30], [4, 0.2], [4, 1], 0.2 mmol was recorded at gadolinium. According to this research, we could not only discover the fact that was iodine could effect on MR signal, but also the pattern is different as various sequences compare to gadolinium. Therefore, we expect useful diagnostic MR image in clinical field with this quantitative data for deciding protocol regarding MRI and CT scan order.

• Journal of IKEEE
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• v.23 no.4
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• pp.1461-1464
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• 2019

In this paper, we propose the development of embedded board for integrated radiation exposure protection fireman's life-saving alarm capable of location tracking and radiation measurement. The proposed techniques consist of signal processing unit, communication unit, power unit, main control unit. Signal processing units apply shielding design, noise reduction technology and electromagnetic wave subtraction technology. The communication unit is designed to communicate using the wifi method. In the main control unit, power consumption is reduced to a minimum, and a high performance system is formed through small, high density and low heat generation. The proposed techniques are equipment operated by exposure to poor conditions, such as disaster and fire sites, so they are designed and manufactured for external appearance considering waterproof and thermal endurance. The proposed techniques were tested by an authorized testing agency to determine the effectiveness of embedded board. The waterproof grade has achieved the IP67 rating, which can maintain stable performance even when flooded with water at the disaster site due to the nature of the fireman's equipment. The operating temperature was measured in the range of -10℃ to 50℃ to cope with a wide range of environmental changes at the disaster site. The battery life was measured to be available 144 hours after a single charge to cope with emergency disasters such as a collapse accident. The maximum communication distance, including the PCB, was measured to operate at 54.2 meters, a range wider than the existing 50 meters, at a straight line with the command-and-control vehicle in the event of a disaster. Therefore, the effectiveness of embedded board for embedded board for integrated radiation exposure protection fireman's life-saving alarm has been demonstrated.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.58-68
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• 2006

This work proposes a 10b 250MS/s $1.8mm^2$ 85mW 0.13um CMOS A/D Converter (ADC) for high-performance integrated systems such as next-generation DTV and WLAN simultaneously requiring low voltage, low power, and small area at high speed. The proposed 3-stage pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The input SHA maintains 10b resolution with either gate-bootstrapped sampling switches or nominal CMOS sampling switches. The SHA and two MDACs based on a conventional 2-stage amplifier employ optimized trans-conductance ratios of two amplifier stages to achieve the required DC gain, bandwidth, and phase margin. The proposed signal insensitive 3-D fully symmetric capacitor layout reduces the device mismatch of two MDACs. The low-noise on-chip current and voltage references can choose optional off-chip voltage references. The prototype ADC is implemented in a 0.13um 1P8M CMOS process. The measured DNL and INL are within 0.24LSB and 0.35LSB while the ADC shows a maximum SNDR of 54dB and 48dB and a maximum SFDR of 67dB and 61dB at 200MS/s and 250MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 85mW at 250MS/s at a 1.2V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.48-57
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• 2006

This work describes a 12b 200KHz 0.52mA $0.47mm^2$ algorithmic ADC for sensor applications such as motor controls, 3-phase power controls, and CMOS image sensors simultaneously requiring ultra-low power and small size. The proposed ADC is based on the conventional algorithmic architecture with recycling techniques to optimize sampling rate, resolution, chip area, and power consumption. The input SHA with eight input channels for high integration employs a folded-cascode architecture to achieve a required DC gain and a sufficient phase margin. A signal insensitive 3-D fully symmetrical layout with critical signal lines shielded reduces the capacitor and device mismatch of the MDAC. The improved switched bias power-reduction techniques reduce the power consumption of analog amplifiers. Current and voltage references are integrated on the chip with optional off-chip voltage references for low glitch noise. The employed down-sampling clock signal selects the sampling rate of 200KS/s or 10KS/s with a reduced power depending on applications. The prototype ADC in a 0.18um n-well 1P6M CMOS technology demonstrates the measured DNL and INL within 0.76LSB and 2.47LSB. The ADC shows a maximum SNDR and SFDR of 55dB and 70dB at all sampling frequencies up to 200KS/s, respectively. The active die area is $0.47mm^2$ and the chip consumes 0.94mW at 200KS/s and 0.63mW at 10KS/s at a 1.8V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.3
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• pp.43-53
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• 2003

Unlike in analog display devices, the physical screen resolution in digital devices are fixed from the manufacturing. It is a weak point on digital devices. The screen resolution displayed in digital display devices is varied. Thus, interpolation or decimation of the resolution on the display is needed to make the input pixels equal to the screen resolution., This process is called image scaling. Many researches have been developed to reduce the hardware cost and distortion of the image of image scaling algorithm. In this paper, we proposed a Winscale algorithm. which modifies the scale up/down in continuous domain to the scale up/down in discrete domain. Thus, the algorithm is suitable to digital display devices. Hardware implementation of the image scaler is performed using Verilog XL and chip is fabricated in a 0.5${\mu}{\textrm}{m}$ Samsung SOG technology. The hardware costs as well as the scalabilities are compared with the conventional image scaling algorithms that are used in other software. This Winscale algorithm is proved more scalable than other image-scaling algorithm, which has similar H/W cost. This image-scaling algorithm can be used in various digital display devices that need image scaling process.

• Journal of Plant Biotechnology
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• v.42 no.3
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• pp.204-214
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• 2015

SHI-RELATED SEQUENCE (SRS) genes are plant-specific transcription factors that contain a zinc-binding RING finger motif, which play a critical role in plant growth and development. Among Brassica rapa SRS genes, BrSRS7 and BrLRP1 genes, isolated from shoot apical regions are important regulators of plant growth and development. In order to explore the function of BrSRS genes in horticultural plant growth and development, two constructs containing BrSRS7 and BrLRP1 under the control of a cauliflower mosaic virus 35S promoter were introduced into petunia by Agrobacterium-mediated transformation. The resulting transgenic plants were dwarf and compact plants with reduced plant height and diameter. Additionally, these transgenic plants had upward-curled leaves of narrow width and short internodes. Interestingly, the flower shapes of petunia were different among transgenic plants harboring different kinds of SRS genes. These phenotypes were stably inherited through generations $T_2$ and $T_3$. Semi-quantitative RT-PCR analyses of transgenic plants revealed that BrSRS7 and BrLRP1 regulate expression of gibberellin (GA)- and auxinrelated genes, PtAGL15- and PtIAMT1-related, involved in shoot morphogenesis. These results indicate that the overexpression of BrSRS7 and BrLRP1 genes suppressed the growth and development of petunia by regulating expression of GA- and auxin-related genes. From these data, we deduce that BrSRS7 and BrLRP1 genes play an important role in the regulation of plant growth and development in petunia. These findings suggest that transformation with the BrSRS genes can be applied to other species as a tool for growth retardation and modification of plant forms.

• Journal of Plant Biotechnology
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• v.36 no.1
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• pp.30-37
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• 2009

Tissue-type plasminogen activator (t-PA) is a thrombolytic agent important in fibirn clot lysis. T-PA causes fibirn-specific plasminogen activation. Six binary vectors harboring t-PA and its derivative genes were cloned and expressed in transgenic alfalfa plants. The insertion of the t-PA and its derivative genes in genomic DNA of alfalfa plants was confirmed by PCR. The presence of the t-PA and its derivative transcripts in total RNAs of the transgenic alfalfa leaves was verified by RT-PCR. ELISA experiments demonstrated that the highest level of recombinant t-PA expression was $75.1{\mu}g$/ total soluble protein (mg) in alfalfa plants. The amount of recombinant t-PA and its derivative proteins in transgenic plants was estimated to range from 9.7 to $39.5{\mu}g$/ total soluble proteins (mg). Western blot analysis of the transformed alfalfa leaves revealed bands of approximately 68-kDa recombinant t-PA and its derivative proteins. The fibrinolysis of recombinant t-PA and its derivative proteins was confirmed by a fibrin plate assay (range from 3.2 to 8.1 cm). The results presented provide information for the development of an additional production of recombinant human proteins having pharmaceutical applications using transgenic plants.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.40 no.5
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• pp.312-321
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• 2003

In this paper, we implement robot which are ability to recognize obstacles and moving automatically to destination. we present two results in this paper; hardware implementation of image processing board and software implementation of visual feedback algorithm for a self-controlled robot. In the first part, the mobile robot depends on commands from a control board which is doing image processing part. We have studied the self controlled mobile robot system equipped with a CCD camera for a long time. This robot system consists of a image processing board implemented with DSPs, a stepping motor, a CCD camera. We will propose an algorithm in which commands are delivered for the robot to move in the planned path. The distance that the robot is supposed to move is calculated on the basis of the absolute coordinate and the coordinate of the target spot. And the image signal acquired by the CCD camera mounted on the robot is captured at every sampling time in order for the robot to automatically avoid the obstacle and finally to reach the destination. The image processing board consists of DSP (TMS320VC33), ADV611, SAA7111, ADV7l76A, CPLD(EPM7256ATC144), and SRAM memories. In the second part, the visual feedback control has two types of vision algorithms: obstacle avoidance and path planning. The first algorithm is cell, part of the image divided by blob analysis. We will do image preprocessing to improve the input image. This image preprocessing consists of filtering, edge detection, NOR converting, and threshold-ing. This major image processing includes labeling, segmentation, and pixel density calculation. In the second algorithm, after an image frame went through preprocessing (edge detection, converting, thresholding), the histogram is measured vertically (the y-axis direction). Then, the binary histogram of the image shows waveforms with only black and white variations. Here we use the fact that since obstacles appear as sectional diagrams as if they were walls, there is no variation in the histogram. The intensities of the line histogram are measured as vertically at intervals of 20 pixels. So, we can find uniform and nonuniform regions of the waveforms and define the period of uniform waveforms as an obstacle region. We can see that the algorithm is very useful for the robot to move avoiding obstacles.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.60-68
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• 2009

This work proposes a 10b 200MS/s 65nm CMOS ADC for high-definition video systems such as HDTV requiring high resolution and fast operating speed simultaneously. The proposed ADC employs a four-step pipeline architecture to minimize power consumption and chip area. The input SHA based on four capacitors reduces the output signal range from $1.4V_{p-p}$ to $1.0V_{p-p}$ considering high input signal levels at a low supply voltage of 1.2V. The proposed three-stage amplifiers in the input SHA and MDAC1 overcome the low output resistance problem as commonly observed in a 65nm CMOS process. The proposed multipath frequency-compensation technique enables the conventional RNMC based three-stage amplifiers to achieve a stable operation at a high sampling rate of 200MS/s. The conventional switched-bias power-reduction technique in the sub-ranging flash ADCs further reduces power consumption while the reference generator integrated on chip with optional off-chip reference voltages allows versatile system a locations. The prototype ADC in a 65nm CMOS technology demonstrates a measured DNL and INL within 0.19LSB and 0.61LSB, respectively. The ADC shows a maximum SNDR of 54.BdB and 52.4dB and a maximum SFDR of 72.9dB and 64.8dB at 150MS/S and 200MS/s, respectively. The proposed ADC occupies an active die area of $0.76mm^2$ and consumes 75.6mW at a 1.2V supply voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.75-85
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• 2009

This work proposes a 13b 100MS/s 0.13um CMOS ADC for 3G communication systems such as two-carrier W-CDMA applications simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs a four-step pipeline architecture to optimize power consumption and chip area at the target resolution and sampling rate. Area-efficient high-speed high-resolution gate-bootstrapping circuits are implemented at the sampling switches of the input SHA to maintain signal linearity over the Nyquist rate even at a 1.0V supply operation. The cascode compensation technique on a low-impedance path implemented in the two-stage amplifiers of the SHA and MDAC simultaneously achieves the required operation speed and phase margin with more reduced power consumption than the Miller compensation technique. Low-glitch dynamic latches in sub-ranging flash ADCs reduce kickback-noise referred to the differential input stage of the comparator by isolating the input stage from output nodes to improve system accuracy. The proposed low-noise current and voltage references based on triple negative T.C. circuits are employed on chip with optional off-chip reference voltages. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.70LSB and 1.79LSB, respectively. The ADC shows a maximum SNDR of 64.5dB and a maximum SFDR of 78.0dB at 100MS/s, respectively. The ABC with an active die area of $1.22mm^2$ consumes 42.0mW at 100MS/s and a 1.2V supply, corresponding to a FOM of 0.31pJ/conv-step.