• Aerospace Engineering and Technology
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• v.2 no.1
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• pp.73-79
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• 2003

Usual satellite design adopts hardware Error Detection and Correction (EDAC) circuitary for memory elements to endure proper operation in space radiation environment and periodic read-back(scrubbing) scheme to remove errors occurred and to prevent further accumulation of errors, in parallel, But lack of detail radiation test data upset rates of KOMPSAT-2 mass storage was estimated very worse compared to that of KOMPSAT-1, which was evaluated from very precise radiation test. Although upset rates were evaluated enough low to accommodate by KOMPSAT-2 Flight Software, hardware scrubbing scheme is studied to shorten scrubbing time as well. This paper describes hardware scrubbing architecture having minimum 1.88 minutes scrubbing interval over 1 Gbits memory.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.6C
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• pp.562-571
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• 2010

Forward error correction (FEC) coding schemes using iterative soft decision detection (SDD) information are mandatory in most of the next generation wireless communication system, in order to combat inevitable channel imparirnents. At the same time, space-time block coding (STBC) schemes are used for the diversity gain. Therefore, SDD information has to be fed into FEC decoder. In this paper, we propose efficient SDD methods for turbo-coded STBC system using high order modulation such as QAM. We present simulation results of various SDD schemes for turbo-coded STBC systems, and show that the proposed methods can provide almost approximating performance to maximum likelihood detection with much less computational load.

• Bulletin of the Society of Naval Architects of Korea
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• v.33 no.2
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• pp.41-48
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• 1996

함정용 탑재장비의 내충격 성능평가 기술분야에 대한 국내의 연구경험이 일천하여 미해군을 비롯한 선진군사강국의 기술구준에 도달하기 위해서는 해결해야 할 과제가 많이 남아있지만, 그 동안의 선박진동분야에서 축적한 구조동력학 분야의 국내기술을 바탕으로 접근해 간다면 그렇게 어려운 문제만은 아니다. 따라서 최근, 이 분야에 대한 국내의 활발한 연구활동을 시발점으로 하여 보다 심도있고 지속적인 연구를 수행한다면 한국해군 함정 및 탑재장비의 내충격 설계기술 자립을 머지 않아 이를 수 있으리라 생각한다. 이를 위해서 이 분야에 대한 국내연구진의 더 많은 노력과 한국해군의 적극적인 지원을 기대한다.

• Journal of the Korean Institute of Telematics and Electronics T
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• v.35T no.1
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• pp.59-66
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• 1998

In this paper, the high-speed decoder for RS(Reed-Solomon) code, one of the most popular error correcting code, is implemented using VHDL. This RS decoder is designed in transform domain instead of most time domain. Because of the simplicity in structure, transform decoder can be easily realized VLSI chip. Additionally the pipeline architecture, which is similar to a systolic array is applied for all design. Therefore, This transform RS decoder is suitable for high-rate data transfer. After synthesis with FPGA technology, the decoding rate is more 43 Mbytes/s and the area is 1853 LCs(Logic Cells). To compare with other product with pipeline architecture, this result is admirable. Error correcting ability and pipeline performance is certified by computer simulation.

• ICROS
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• v.4 no.3
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• pp.15-21
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• 1998

현재 컴퓨터 기억장치로 사용되는 것으로 SRAM, DRAM, flash memory 등과 같은 반도체 메모리와 자기를 이용한 하드디스크, 플로피디스크, 테이프 그리고 광자기 디스크 등이 있다. 이 중에서 보조 기억장치로 가장 많이 사용되는 시스템이 하드디스크 드라이브(HDD)이다. 데이터를 기록 재생할 수 있으며, 데이터의 보관, 데이터의 접근속도 등을 고려할 때 가격대비 성능 면에서 HDD를 능가하는 기억장치가 아직까지 없다. 본 고에서는 퍼스널컴퓨터나 웍스테이션에 사용되는 HDD의 기술동향을 제어기술 관점에서 서술하고자 한다.

• Information and Communications Magazine
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• v.25 no.9
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• pp.41-48
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• 2008

펨토셀(Femtocell), 가정용 기지국(Home Base Station 혹은 Home e-NodeB) 등 여러 가지 이름으로 불리고 있는 초소형 기지국은 셀룰러 망과 동일한 기술을 이용하여 동일 혹은 인접 주파수 영역에서 서비스를 제공하는 일반 사용자 장비이다. 이미 규격화가 완료되어 서비스 중인 무선 접속기술들은 초소형 기지국을 효과적으로 지원하지 못하고 있는 반면 차세대 무선 통신 기술로 논의가 진행 중인 LTE(Long Term Evolution) 시스템에서는 가정용 초소형 기지국을 논의 처음부터 고려하여 무선 접속 기술 및 시스템을 설계하고 있다. 본 고에서는 현재 LTE 시스템에서 펨토셀을 지원하기 위해 고려 중인 다양한 제안들과 결정 사항들을 알아본다.

• Journal of Ocean Engineering and Technology
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• v.33 no.1
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• pp.98-98
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• 2019

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.9
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• pp.39-48
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• 2004

Turbo codes, whose performance in bit error rate is close to the Shannon limit, have been adopted as a part of standard for the third-generation high-speed wireless data services. Iterative Turbo decoding results in decoding delay and high power consumption. As wireless communication systems can only use limited power supply, low power design techniques are essential for mobile device implementation. This paper proposes new effective criteria for stopping the iteration process in turbo decoding to reduce power consumption. By setting two stopping criteria, decodable threshold and undecodable threshold, we can effectively reduce the number of decoding iterations with only negligible error-correcting performance degradation. Simulation results show that the number of unsuccessful error-correction can be reduced by 89% and the number of decoding iterations can be reduced by 29% on the average among 12500 simulations when compared with those of an existing typical method.

• Journal of the Korea Society of Computer and Information
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• v.25 no.1
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• pp.29-36
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• 2020

Wear-leveling techniques and Error Correction Codes (ECCs) are essential for the improvement of the reliability and durability of flash memories. Low-Density Parity-Check (LDPC) codes have higher error correction capabilities than conventional ECCs and have been applied to various flash memory-based storage devices. Conventional wear-leveling schemes using only the number of Program/Erase (P/E) cycles are not enough to reflect the actual aging differences of flash memory components. This paper introduces an actual aging measurement scheme for flash memory wear-leveling using LDPC decoding information. Our analysis, using error-rates obtained from an flash memory module, shows that LDPC decoding information can represent the aging degree of each block. We also show the effectiveness of the wear-leveling based on the proposed scheme through wear-leveling simulation experiments.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.4
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• pp.430-435
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• 2018

In this paper, an improved decoding scheme for low-complexity parity-check(LCPC) code with small code length is proposed. The LCPC code is less complex than the turbo code or low density parity check(LDPC) code and requires less memory, making it suitable for communication between internet-of-things(IoT) devices. The IoT devices are required to have low complexity due to limited energy and have a low end-to-end delay time. In addition, since the packet length to be transmitted is small and the signal processing capability of the IoT terminal is small, the LCPC coding system should be as simple as possible. The LCPC code can correct all single errors and correct some of the two errors. In this paper, the proposed decoding scheme improves the bit error rate(BER) performance without increasing the complexity by correcting both errors using the soft value of the modulator output stage. As a result of the simulation using the proposed decoding scheme, the code gain of about 1.1 [dB] was obtained at the bit error rate of $10^{-5}$ compared with the existing decoding method.