• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.6A
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• pp.640-647
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• 2006

This paper describes a design of AES-based CCMP(Counter mode with CBC-MAC Protocol) core for IEEE 802.11i wireless LAN security. To maximize the performance of CCMP core, two AES cores are used, one is the counter mode for data confidentiality and the other is the CBC node for authentication and data integrity. The S-box that requires the largest hardware in ARS core is implemented using composite field arithmetic, and the gate count is reduced by about 27% compared with conventional LUT(Lookup Table)-based design. The CCMP core was verified using Excalibur SoC kit, and a MPW chip is fabricated using a 0.35-um CMOS standard cell technology. The test results show that all the function of the fabricated chip works correctly. The CCMP processor has 17,000 gates, and the estimated throughput is about 353-Mbps at 116-MHz@3.3V, satisfying 54-Mbps data rate of the IEEE 802.11a and 802.11g specifications.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.37 no.10
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• pp.955-966
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• 2009

DES method is applied to an axisymmetric base flow at supersonic mainstream. The model is based on the Spalart-Allmaras (S-A) turbulence model in the RANS mode, and is based on the subgrid scale model in the Large-eddy simulation (LES) mode. Accurate predictions of the base flowfield and base pressure are successfully achieved by using the DES methodology which is less expensive than LES. Flow properties at the edge of base, such as boundary layer thickness, momentum thickness and skin fraction are compared with Dutton et al [experimental data to proper prediction of base flowfiled. From the present results, The DES accurately resolves the physics of unsteady turbulent motions, such as shear layer rollup, large-eddy motions in the downstream region and small eddy motions inside the recirculating region. Moreover, The present results of using an empirical constant $C_{DES}$ of 1.2 shows good agreement with experimental data than conventional empirical constant $C_{DES}$ of 0.65.

• Journal of the Korean Society for Railway
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• v.20 no.3
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• pp.349-355
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• 2017

Failures of railway systems can result in train delays or accidents, and therefore high reliability is required to ensure safety of railway systems. To improve reliability, railway systems are designed with redundant systems so that the standby system will continue to function normally even if the primary system fails. Generally, overall system reliability can be evaluated by the reliabilities of the parts of the whole system and the reliability of the redundant system considering common failures in case of each system is not conform physical, functional and process independent. In this study, the reliability of the hot-standby sparing system is analyzed the independent systems and dependent systems with common failures. The reliability for the standby system can be effectively analysed using Markov models, which can model the redundant configuration and the state transition.

• Journal of Advanced Navigation Technology
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• v.26 no.5
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• pp.358-364
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• 2022

The Inter Communication System for avionics is in charge of processing all voice signals that internal calls between Pilot and Co-pilot, internal calls between Pilots and Crews, external calls through communication equipment such as Ultra/Very High Frequency Receiver/Transmitter(U/VHF RT), audio signal monitoring for navigation and mission equipment such as VHF Omnidirectional Range/Instrument Landing System(VOR/ILS), Tactical Air Navigation(TACAN), audio signal output for voice recording to Flight Data Recorder(FDR) and Data Transfer System(DTS), and warning/caution audio signal generate about the status and threat of aircraft. Because Inter Communication System for avionics is sensitive to noise in the case of analog audio signals, a redundant design that can protect audio signal from electromagnetic noise inside/outside of aircraft is required for the mission of pilots and crews. In this paper, Normal/Back-up operation mode and redundancy design plan based on digital method for the redundancy of the digital Inter Communication System for avionics and manufacturing, verification results are described.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.42 no.2
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• pp.144-149
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• 2014

A ground firing test for hot-fire performance evaluation according to the characteristic length($L^*$) variation of thrust chamber was carried out for the hydrazine thruster which may be employed in space launch vehicles. A scrutiny into the performance characteristics of each thruster is made in terms of thrust, specific impulse, response characteristics, and characteristic velocity at steady-state firing mode with propellant inlet pressure of 2.41 MPa (350 psia). Through the test results, it has been verified that performance of characteristic velocity and specific impulse degrades as the characteristic length deviates from that of the standard model. Thus, it is confirmed that the thrust chamber configuration of standard model was suitably designed for the requirement specified.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.111-118
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• 2008

In this paper, novel latch-up prevention method that employs power-up sequential switches has been proposed to relieve latch-up problem in liquid crystal display (LCD) driver ICs. These sequential switches are inserted in the 2'nd and 3'rd boosting stages, and are used to short the emitter-base terminals of parasitic p-n-p-n circuit before relevant boosting stages are activated during power-up sequence. To verily the performance of the proposed method, test chips were designed and fabricated in a 0.13-um CMOS process technology. The measurement results indicated that, while the conventional LCD driver If entered latch-up mode at $50^{\circ}C$ accompanying a significant amount of excess current, the driver IC adopting the proposed method showed no latch-up phenomenon up to $100^{\circ}C$ and maintained normal current level of 0.9mA.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.2
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• pp.47-54
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• 2008

In this paper, we studied how and why did abnormal IMC growth at component affect on board level mechanical reliability. First, interfacial reactions between Sn2.5Ag0.5Cu solder and electrolytic Ni/Au UBM of component side were investigated with reflow times and thermal aging time. Also, to compare mechanical reliability of component level, shear energy was evaluated using the ball shear test conducted with variation of shear tip speed. Finally, to evaluate mechanical reliability of board level, we surface-mounted component fabricated with each condition on PCB side. After conducting of 3 point bending test and impact test, we confirmed solder joint crack mode using cross-sectioning and dye & pry penetration method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.4
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• pp.73-79
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• 2007

In this paper the proposed transactor is customized and a generator which roles of automatically generating the transactor according to DUT(Design Under Test)'s input and output is implemented. The customized transactor is designed by rearranging the signals of depending on DUT and transactor protocol which consists of signals of the PCI interface between host computer and FPGA(Field Programmable Gate Array). The implemented automatic generator of transactor generates a Verilog code of transactor by adding DUT's information about input and output ports. Performance and normal working of the generated transactor has been verified by experiments with some verified hardware IPs. Also, an efficiency of the transactor has been verified by comparing with user's manually designed transactor and generated transactor. Moreover, the generator's flexibility has been verified for DUT's information of variable input and output. In case of using the implemented generator, a design time of transactor is reduced.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.49 no.7
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• pp.32-38
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• 2012

In this paper, to eliminate intersymbol interference of the received signal due to multipath propagation, a parallel equalization algorithm using two error estimation functions is proposed. In the proposed algorithm, multilevel two-dimensional signals are considered as equivalent binary signals, then error signals are estimated using the sigmoid nonlinearity effective at the initial phase equalization and threshold nonlinearity with high steady-state performance. The two errors are scaled by a weight depending on the relative accuracy of the two error estimations, then two filters are updated differentially. As a result, the combined output of two filters was to be the optimum value, fast convergence at initial stage of equalization and low steady-state error level were achieved at the same time thanks to the combining effect of two operation modes smoothly. Usefulness of the proposed algorithm was verified and compared with the conventional method through computer simulations.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.9
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• pp.1957-1967
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• 1997

Adaptive channel equlization accomplished without resorting to a training sequence is known as blind equalization. In this paper, in order to reduce the speed of the convergence and the steady-state mean squared error simultaneously, we propose the multi-stage RD(radius-directed) algorithm derived from the combination of the constant modulus algorithm and the radius-directed algorithm. In the starting stage, multi-stage RD algorithm are identical to the constant modulus algorithm which guarantees the convergence of the equalizer. As the blind identical to the constant modulus algorithm which guarantees the convergence of the equalizer. As the blind equalizer converges, the number of the level of the quantizers is increased gradually, so that the proposed algorithm operate identical to the radius-directed algorithm which leads to the low error power after the covnergence. Therefore, the multi-stage RD algorithm obtains fast convergence rage and low steady stage mean square error.