• Journal of KIISE
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• v.42 no.10
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• pp.1280-1285
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• 2015

Many hardware-based regular expression matching architectures are proposed for high performance matching. In particular, regular expression processors such as ReCPU and SMPU perform pattern matching in a similar approach to that used in general purpose processors, which provide the flexibility when updating patterns. However, these processors are inefficient in performing class matching since they do not provide character class matching capabilities. This paper proposes an instruction set and architecture of a regular expression matching processor, which can support character class matching. The proposed processor can efficiently perform character class matching since it includes character class, character range, and negated character class matching capabilities.

• KIISE Transactions on Computing Practices
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• v.23 no.2
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• pp.97-103
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• 2017

Many hardware-based regular expression matching architectures have been proposed for high-performance matching. In particular, regular expression processors, which perform pattern matching by treating the regular expressions as the instruction sequence like general purpose processors, have been proposed. After instruction sequence and data are provided in the instruction memory and data memory, respectively, a regular expression processor can perform pattern matching. To use a regular expression processor as a coprocessor, we need the host interface to transfer the instruction and data into the memory of a regular expression processor. In this paper, we design and implement the host interface between a host and a regular expression processor in the DE1-SoC board and the application program interface. We verify the operations of the host interface and a regular expression processor by executing the application programs which perform pattern matching using the application program interface.

• Journal of the Korea Society of Computer and Information
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• v.16 no.5
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• pp.13-22
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• 2011

Network Intrusion Detection Systems use regular expression to represent malicious packets and hardware-based pattern matching is required for fast deep packet inspection. Although hardware architectures for implementing constraint repetition operators such as {10} were recently proposed, they have some limitation. In this paper, we propose hardware architecture supporting constraint repetitions of general regular expression sub-patterns with lower logic complexity. The subpatterns supported by the proposed contraint repetition architecture include general regular expression patterns as well as a single character and fixed length patterns. With the proposed building block, we can implement more efficiently regular expression pattern matching hardwares.

• Journal of IKEEE
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• v.22 no.1
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• pp.87-92
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• 2018

Like CPUs, regular expression processors that perform regular expression pattern matching using instructions have been proposed recently. Of these, only REMPc provides features for character class matching. In this paper, we propose an architecture for efficient character class matching in a regular expression processor, which use character class bitmap format in a instruction operand field and implement the hard-wired character class comparator for several frequently used character classes. Using the proposed method, most of the character classes used in Snort rule can be represented by an operand or an instruction. Thus, character class matching can be performed more efficiently in the proposed archiecture than in REMPc.

• 한국어정보학회:학술대회논문집
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• 2017.10a
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• pp.264-266
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• 2017

본 연구는 리마인더 앱을 위한 효과적인 시간 표현 분석 방법을 제안한다. 시간 표현 분석을 위한 정규식 패턴을 이용하여 사용자 발화 텍스트로부터 시간 정보를 분석하고 시간 표현 유형에 따라 절대적 시간 정보로 변환한다. 제안한 방법은 정규식 패턴을 이용한 시간 표현 분석 기법으로 시스템의 유지 관리가 용이하고 정보량이 많은 패턴과의 매칭을 위해 효과적이다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.1B
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• pp.47-55
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• 2009

In recent network intrusion detection systems, regular expressions are used to represent malicious packets. In order to process incoming packets through high speed networks in real time, we should perform hardware-based pattern matching using the configurable device such as FPGAs. However, operating speed of FPGAs is slower than giga-bit speed network and so, multi-byte processing per clock cycle may be needed. In this paper, we propose a hardware architecture of multi-byte based regular expression pattern matching and implement the pattern matching circuit generator. The throughput improvements in four-byte based pattern matching circuit synthesized in FPGA for several Snort rules are $2.62{\sim}3.4$ times.

• The Journal of the Korea Contents Association
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• v.8 no.2
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• pp.33-40
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• 2008

In various manners, string pattern matching algorithm has been proven for prominence in speed of searching particular queries and keywords. Whereas, the existing algorithms are limited in terms of various pattern. In this paper, regular expression has been utilized to improve efficiency of pattern matching through efficient execution towards various pattern of queries including particular keywords. Such as this research would enable to search various harmful string pattern more efficiently, rather than matching simple keywords, which also implies excellent speed of string pattern matching compared to that of those existing algorism. In this research, the proposed string search engine generated from the LEX are more efficient than BM & AC algorithm for a string patterns search speed in cases of 1000 with more than patterns, but we have got similar results for the keywords pattern matching.

• Annual Conference on Human and Language Technology
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• 2017.10a
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• pp.264-266
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• 2017

본 연구는 리마인더 앱을 위한 효과적인 시간 표현 분석 방법을 제안한다. 시간 표현 분석을 위한 정규식 패턴을 이용하여 사용자 발화 텍스트로부터 시간 정보를 분석하고 시간 표현 유형에 따라 절대적 시간 정보로 변환한다. 제안한 방법은 정규식 패턴을 이용한 시간 표현 분석 기법으로 시스템의 유지 관리가 용이하고 정보량이 많은 패턴과의 매칭을 위해 효과적이다.

• Annual Conference on Human and Language Technology
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• 2007.10a
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• pp.150-157
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• 2007

본 논문에서는 의존 구조 매칭과 약한 지도식 학습 방법을 적용하여 텍스트에서 IS-A 관계를 자동으로 추출하고 순위화하는 방법을 제안한다. 텍스트에서 잠재적인 IS-A 관계를 표현하는 [관계 표현, 하위어, 상위어]의 삼진관계 리스트를 추출하고, 관계 표현과 IS-A 관계 인스턴스, IS-A 관계 후보, 사이의 상호 관련성을 이용하여 각각의 점수를 반복적으로 정제한다. 제안한 방법의 대표적인 특징은 다음과 같다. 1) 의존 구조에 기반한 패턴 매칭 방법을 적용하여 정규 표현에 기반한 방법보다 다양한 형태의 삼진관계를 추출할 수 있고, 2) 도메인 코퍼스에서 통계적으로 추출한 어휘 사이의 관련성 정보를 이용하여 도메인에 적합한 IS-A 관계 인스턴스의 순위를 높일 수 있으며, 3) 관계 표현과 관계 인스턴스의 점수를 상호 관련성에 기반한 방법으로 반복적으로 점수화하여 IS-A 관계 인스턴스 사이의 변별력을 높일 수 있다. 실험에서 순위화된 관계 인스턴스는 전문가의 판단과 66%이상 일치함을 보였고, 의존 구조를 이용한 유연한 패턴 매칭 방법은 정규표현을 이용한 방법보다 43.6%의 추가적인 삼진관계를 추출하였다.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.23 no.3
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• pp.395-404
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• 2013

A pattern matching algorithm plays an important role in traffic identification and classification based on predefined patterns for intrusion detection and prevention. As attacks become prevalent and complex, current patterns are written using regular expressions, called regexes, which are expressed into the deterministic finite automata(DFA) due to the guaranteed worst-case performance in pattern matching process. Currently, because of the increased complexity of regex patterns and their large number, memory-efficient DFA from states reduction have become the mainstay of pattern matching process. However, most of the previous works have focused on reducing only the number of states on a single automaton, and thus there still exists a state blowup problem under the large number of patterns. To solve the above problem, we propose a new state compression algorithm that merges states on multiple automata. We show that by merging states with the same input character on multiple automata, the proposed algorithm can lead to a significant reduction of the number of states in the original DFA by as much as 40.0% on average.