• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.5
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• pp.359-369
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• 2020

In this paper, we proposed a charge pump (CP) circuit that has a wide operating range while reducing the current mismatch for the PLL that generates the main clock of the CMOS X-Ray detector. The operating range and current mismatch of the CP circuit are determined by the characteristics of the current source circuit for the CP circuit. The proposed CP circuit is implemented with a wide operating current mirror bias circuit to secure a wide operating range and a cascode structure with a large output resistance to reduce current mismatch. The proposed wide operating range cascode CP circuit was fabricated as a chip using a 350nm CMOS process, and current matching characteristics were measured using a source measurement unit. At this time, the power supply voltage was 3.3 V and the CP circuit current ICP = 100 ㎂. The operating range of the proposed CP circuit is △VO_Swing=2.7V, and the maximum current mismatch is 5.15 % and the maximum current deviation is 2.64 %. The proposed CP circuit has low current mismatch characteristics and can cope with a wide frequency range, so it can be applied to systems requiring various clock speed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.11
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• pp.2627-2635
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• 2013

In this paper micro-scale solar energy harvesting system with a new MPPT control are proposed. In conventional solar energy harvesting systems, continuous perturbation techniques of the clock frequency or duty cycle of a power converter have been used to implement MPPT(Maximum Power Point Tracking) control. In this paper, we propose a new MPPT technique to control the duty cycle of a power switch powering a power converter. The proposed circuit is designed in $0.35{\mu}m$ CMOS process, and the designed chip area including pads is $770{\mu}m{\times}800{\mu}m$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.130-134
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• 2008

This paper presents a clock and data recovery(CDR) using a quarter-rate technique. The proposed CDR helps reduce the VCO frequency and is thus advantageous for high speed application. It can achieve a low jitter operation and extend the pull-in range without a reference clock. The CDR consists of a quarter-rate bang-bang type phase detector(PD) quarter-rate frequency detector(QRFD), two charge pumps circuits(CPs), low pass filter(LPF) and a ring voltage controlled oscillator(VCO). The Proposed CDR has been fabricated in a standard $0.18{\mu}m$ 1P6M CMOS technology. It occupies an active area $1{\times}1mm^2$ and consumes 98 mW from a single 1.8 V supply.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.3
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• pp.549-557
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• 2012

In this paper an on-chip photo energy harvesting system with MPPT(Maximum Power Point Tracking) control is proposed. The ISC(Integrated Solar Cell) is implemented using p-diff/n-well diodes available in CMOS processes. MPPT control is implemented using the linear relationship between the open-circuit voltage of a PV(Photovoltaic) cell and its MPP(Maximum Power Point) voltage such that a small pilot PV cell can track the MPP of a main PV cell in real time. Simulation results show that the designed circuit with the MPPT control delivers the MPP voltage to load even though the load is heavy such that the load circuit can operate properly. The proposed circuit is designed in 0.18um CMOS process. The designed main PV cell and pilot PV cell occupy $8mm^2$ and $0.4mm^2$ respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.1
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• pp.56-63
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• 2008

This paper describes a 12 bit 1GS/s current mode segmented DAC for WCDMA communication. The proposed circuit in this paper employes segmented structure which consists of 4bit binary weighted structure in the LSB and 4bit thermometer decoder structure in the mSB and MSB. The proposed DAC uses delay time compensation circuits in order to suppress performance decline by delay time in segmented structure. The delay time compensation circuit comprises of phase frequency detector, charge pump, and control circuits, so that suppress delay time by binary weighted structure and thermometer decoder structure. The proposed DAC uses CMOS $0.18{\mu}m$ 1-poly 6-metal n-well process, and measured INL/DNL are below ${\pm}0.93LSB/{\pm}0.62LSB$. SFDR is approximately 60dB and SNDR is 51dB at 1MHz input frequency. Single DAC's power consumption is 46.2mW.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.577-580
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• 2014

In this paper an auto-switching dual-input energy harvesting circuit is proposed. Since the maximum power points of a thermoelectric generator(TEG) output and a vibration device(PEG) output is 1/2 of their open-circuit voltage, an identical MPPT controller can be used for both energy sources. The proposed circuit monitors the outputs of the TEG and PEG, and chooses the energy source generating a higher output using an auto-switching controller, and then harvests the maximum power from the selected device using a MPPT controller. The harvested energy is boosted through a charge pump and stored in a storage capacitor. The stored energy is provided to a load through a PMU(Power Management Unit). The proposed circuit is designed in a $0.35{\mu}m$ CMOS process and its functionality has been verified through extensive simulations. The designed chip occupies $1.4mm{\times}1.2mm$ including pads.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.14 no.1
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• pp.37-42
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• 2021

This paper presents a jitter and phase noise characteristic improved phase-locked loop (PLL) with loop filter voltage detector(LFVD) and frequency voltage converter(FVC). Loop filter output voltage variation is determined through a circuit made of resistor and capacitor. The output signal of a small RC time constant circuit is almost the same as to loop filter output voltage. The output signal of a large RC time constant circuit is the average value of loop filter output voltage and becomes a reference voltage to the added LFVD. The LFVD output controls the current magnitude of sub-charge pump. When the loop filter output voltage increases, LFVD decreases the loop filter output voltage. When the loop filter output voltage decreases, LFVD increases the loop filter output voltage. In addition, FVC also improves the phase noise characteristic by reducing the loop filter output voltage variation. The proposed PLL with LFVD and FVC is designed in a 0.18um CMOS process with 1.8V power voltage. Simulation results show 0.854ps jitter and 30㎲ locking time.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.15 no.2
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• pp.89-94
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• 2022

In this paper, a discrete-time loop filter(DLF) phase-locked loop with a Frequency Fluctuation Converting Circuit(FFCC) has been proposed. Discrete-time loop filter can improve spur characteristic by connecting the charge pump and voltage oscillator discretely unlike a conventional continuous-time loop filter. The proposed PLL is designed to operate stably by the internal negative feedback loop including the SSC acting as a negative feedback to the discrete-time loop filter of the external negative feedback loop. In addition, the phase noise is further improved by reducing the magnitude of the loop filter output voltage variation through the FFCC. Therefore, the magnitude of jitter has been reduced by 1/3 compared to the conventional structure. The proposed phase locked loop has been simulated with Hspice using the 1.8V 180nm CMOS process.

• Journal of Chest Surgery
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• v.38 no.2 s.247
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• pp.101-109
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• 2005

Background: In sudden cardiac arrest, the effective maintenance of coronary artery blood flow is of paramount importance for myocardial preservation as well as cardiac recovery and patient survival. The purpose of this study was to directly compare the effects of pulsatile and non-pulsatile circulation to coronary artery flow and myocardial preservation in cardiac arrest condition. Material and Method: A cardiopulmonary bypass circuit was constructed in a ventricular fibrillation model using fourteen Yorkshire swine weighing $25\~35$ kg each. The animals were randomly assigned to group I (n=7, non-pulsatile centrifugal pump) or group II (n=7, pulsatile T-PLS pump). Extra-corporeal circulation was maintained for two hours at a pump flow of 2 L/min. The left anterior descending coronary artery flow was measured with an ultrasonic coronary artery flow measurement system at baseline (before bypass) and at every 20 minutes after bypass. Serologic parameters were collected simultaneously at baseline, 1 hour, and 2 hours after bypass in the coronary sinus venous blood. The Mann-Whitney U test of STATISTICA 6.0 was used to determine intergroup significances using a p value of < 0.05. Result: The resistance index of the coronary artery was lower in group II and the difference was significant at 40 min, 80 min, 100 min and 120 min (p < 0.05). The mean velocity of the coronary artery was higher in group II throughout the study, and the difference was significant from 20 min after starting the pump (p < 0.05). The coronary artery blood flow was higher in group II throughout the study, and the difference was significant from 40 min to 120 min (p < 0.05) except at 80 min. Serologic parameters showed no differences between the groups at 1 hour and 2 hours after bypass in the coronary sinus blood. Conclusion: In cardiac arrest condition, pulsatile extracorporeal circulation provides more blood flow, higher flow velocity and less resistance to coronary artery than non-pulsatile circulation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.21-31
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• 2010

This paper presents a design of PLL and SSCG for reducing the EMI effect at the electronic machinery and tools for DisplayPort application. This system is composed of the essential element of PLL and Charge-Pump2 and Reference Clock Divider to implement the SSCG operation. In this paper, 270MHz/162MHz dual-mode PLL that can provide 10-phase and 1.35GHz/810MHz PLL that can reduce the jitter are designed for 2.7Gbps/162Gbps DisplayPort application. The jitter can be reduced drastically by combining 270MHz/162MHz PLL with 2-stage 5 to 1 serializer and 1.35GHz PLL with 2 to 1 serializer. This paper propose the frequency divider topology which can share the divider between modes and guarantee the 50% duty ratio. And, the output current mismatch can be reduced by using the proposed charge-pump topology. It is implemented using 0.13 um CMOS process and die areas of 270MHz/162MHz PLL and 1.35GHz/810MHz PLL are $650um\;{\times}\;500um$ and $600um\;{\times}\;500um$, respectively. The VCO tuning range of 270 MHz/162 MHz PLL is 330 MHz and the phase noise is -114 dBc/Hz at 1 MHz offset. The measured SSCG down spread amplitude is 0.5% and modulation frequency is 31kHz. The total power consumption is 48mW.