• Title/Summary/Keyword: 적층 쉘요소

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A Parametric Study of Deflection Analysis of the Prestressed Beams using Finite Element Analysis (유한요소해석을 이용한 프리스트레스트 보의 처짐에 대한 변수 해석)

  • Park, Ha Eun;Choi, Jin Woong;Kim, Min Sook;Lee, Young Hak
    • Journal of the Computational Structural Engineering Institute of Korea
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    • v.28 no.1
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    • pp.39-46
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    • 2015
  • The purpose of this study is to analyze the deflection of the prestressed beams. In this paper, a finite element model for deflections of prestressed beams is presented. Proposed finite element model was verified comparing with existing experimental results, and it showed a good agreement with the experimental results. Also, a parametric study has been conducted to analyze the influence of eccentricity, span-depth ratio, and prestressing force. The finite element model results were compared with hand calculation results. Deflections were increased as the eccentricity decreases, the span-depth ratio increases, and the prestressing force decreases. Hand calculation overestimated the deflection when the eccectricity or prestressing force is too small.

Finite Element Analysis of Wafer Level Warpage with Respect to the Materials of Through-via Layer during RDL Process in 2.xD Package (2.xD Package의 RDL공정 중 Through-via Layer 소재에 따른 Wafer Level Warpage의 유한요소해석)

  • Seungchul Yang;Seongwoo Im;Jihoon Kim;Chanseop Shin;Sanggyu Jang;Sangyul Ha;Jin-Wook Jang
    • Journal of the Microelectronics and Packaging Society
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    • v.31 no.4
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    • pp.64-70
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    • 2024
  • Recently, with increasing demand for high-performance and multifunctional products in semiconductor market, the packaging technology has become critical to integrate a variety of components into a single system. Especially, wafer-level interposer and bridge fabrication methods are considered key components in this field. They can efficiently deliver electrical signals with high I/O density. However, excessive warpage can occur during the process due to thermal mismatch, leading to defects and reduced yield. In this paper, a finite element analysis was performed to predict the wafer warpage during the redistribution layer (RDL) process. The finite element model was created using one quarter of the entire wafer area and used shell elements with a composite type. The model was composed of a Si carrier and a RDL including through-via layer. Simulation results were compared for the different materials of through-via layer in RDL. The simulation was performed from 200℃ to room temperature. Additionally, to analyze the effects of the number of RDL layers, simulation was conducted for both single and multi-layers. Simulation showed the significantly differences result depending on the material type of through-via layer and RDL thickness. These results enabled the identification of optimum combination to minimize the warpage and the temperature factor.