• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.6-12
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• 2010

A sigma-delta modulator based class-D audio amplifier is presented. Parallel digital input is serialized to two-bit output by a fourth-order digital sigma-delta noise shaper. The output of the digital sigma-delta noise shaper is applied to a fourth-order analog sigma-delta modulator whose three-level output drives power switches. The pulse density modulated (PDM) output of the power switches is low-pass filtered by an LC-filter. The PDM output of the power switches is fed back to the input of the analog sigma-delta modulator. The first integrator of the analog sigma-delta modulator is a hybrid of continuous-time (CT) and switched-capacitor (SC) integrator. While the sampled input is applied to SC path, the continuous-time feedback signal is applied to CT path to suppress the noise of the PDM output. The class-D audio amplifier is fabricated in a standard $0.13-{\mu}m$ CMOS process and operates for the signal bandwidth from 100-Hz to 20-kHz. With 4-${\Omega}$ load, the maximum output power is 18.3-mW. The total harmonic distortion plus noise and dynamic range are 0.035-% and 80-dB, respectively. The modulator consumes 457-uW from 1.2-V power supply.

• The KIPS Transactions:PartA
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• v.15A no.3
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• pp.135-140
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• 2008

This paper describes a high-speed CMOS demultiplexer using redundant multi-valued logic (RMVL). The proposed circuit receives serial binary data and is converted to parallel redundant multi-valued data using RMVL. The converted data are reconverted to parallel binary data. By the redundant multi-valued data conversion, the RMVL makes it possible to achieve higher operating speeds than that of a conventional binary logic. The implemented demultiplexer consists of eight integrators. Each integrator is composed of an accumulator, a window comparator, a decoder and a D flip flop. The demultiplexer is designed with TSMC $0.18{\mu}m$ standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation. The demultiplexer is achieved the maximum data rate of 20 Gb/s and the average power consumption of 95.85 mW.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.35 no.12
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• pp.1607-1612
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• 2011

In this study, dynamic analysis of a proportional solenoid valve is performed, and an LQG/LTR controller with an integrator is designed to control the proportional solenoid valve. The dynamic characteristic of a valve is identified using experimental data by employing the frequency-domain modeling technique. The purpose of LQG/LTR control with an integrator is to enhance the system response and to improve the tracking accuracy for a complex input signal. Experimental tests are performed to verify the performance of the controller, and the results prove the high performance of the controller.

• The Transactions of the Korean Institute of Power Electronics
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• v.9 no.4
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• pp.381-389
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• 2004

In this paper, it is suggested that instantaneous compensation PWM control for inverter without the smoothing capacitor Therefore, this inverter system has several advantages. It has small volume and low price to manufacture, decrease trouble rate of inverter, and has power factor correction effect because huge smoothing capacitor-less. And it has compact size control circuit to use analog integrator device. It could make the smoothing capacitor-less inverter for air-blower motor by using the instantaneous compensation PWM controller. This inverter system has small volume and value compare with the conventional VVVF control inverter.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.5B
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• pp.639-644
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• 2001

본 논문에서는 저전압(2V) 동작이 가능하도록 high-swing cascode 방식을 이용한 능동소자를 제안하고, 이를 이용하여 400MHz의 차단주파수 특성을 나타내는 저역통과 능동필터를 설계하였다. 제안된 적분기는 이득특성에 영향을 주는 트랜스컨덕스값을 증가시키기 위해 CMOS 상보형 캐스코드 방식을 이용하여 구성되었다. 0.25$\mu\textrm{m}$ CMOS n-well 공정 파라미터를 이용한 Hspice 시뮬레이션 결과, 제안된 적분기는 2V 공급전압하에서 42dB의 이득값과 200MHz의 단위이득주파수 특성을 나타내었다. 또한 이를 이용하여 설계된 저역통과 능동필터는 400MHz의 차단주파수 특성을 나타내고 368MHz에서 416MHz까지 튜닝이 가능하였다.

• Proceedings of the KIEE Conference
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• 2000.07d
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• pp.3139-3141
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• 2000

전압제어 트랜스컨덕터를 설계하여 튜닝범 위가 넓은 Gm-C 대역통과 필터를 CMOS 공정으로 설계하였다 Gm-C 필터는 트랜스컨덕터와 캐패시터로 구성된 적분기를 기본으로 구현되고 있다. 따라서 트랜스 컨덕터는 출력단에 캐패시터를 연결하였을 때 이상적인적인 적분기의 특성에 가까울수록 필터의 특성이 좋아지고 PLL 구조의 튜닝이 용이해진다. 본 논문에서는 1:3이상의 범위에서 튜닝이 가능하고 PLL을 기본으로한 자동튜닝과 선형전압 튜닝을 조합하여 주파수 제어회로를 설계하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.9 no.1
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• pp.25-29
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• 1984

The active compensation of operational amplifeir is that it compensates the phase shift and the attennation of gain of OP Amp, according as the frequency increases. The compensation circuit is applied to VCVS and interting integrator. For VCVS, the phase shift of proposed compensated circuit is not concern with the frequency and the gain chracteristic is better than the proposde circuit by Soliman, according as the rate of feedback resistors of compensated circuit changes. Voltage follower accomplishies compgnsation using the same circuit. Also, the compensation circuit to increase O-ffactor in inverting integrator is proposed.

• Proceedings of the Korean Magnestics Society Conference
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• 2009.05a
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• pp.220-221
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• 2009

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.2
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• pp.265-276
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• 2017

In this paper, a robust and more accurate trajectory tracking control method for a mobile robot is proposed using WIPDC(Weighted Integral Parallel Distributed Compensation) and T-S Fuzzy disturbance observer. WIPDC reduces the steady state error by adding weighted integral term to PDC. And, T-S Fuzzy disturbance observer makes it possible to estimate and cancel disturbances for a T-S fuzzy model system. As a result, the trajectory tracking controller based on T-S Fuzzy disturbance observer shows robust tracking performance. When the initial postures of a mobile robot and the reference trajectory are different, the initial control inputs to the mobile robot become too large to apply them practically. In this study, also, the problem is solved by designing an initial approach path using a path planning method which employs $B\acute{e}zier$ curve with acceleration limits. Performances of the proposed method are proved from the simulation results.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.43 no.1 s.307
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• pp.39-44
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• 2006

Pattern noise in the Delta-Sigma modulator is a well Known phenomenon that intrigued many circuit designers. These noise appear as the modulator output falls into a cyclic mode of operation. This paper addresses the dependence of these tone signal upon the system topologies. Among the four well known single-stage DSM topologies, namely Cascade of Integrators with Feedback Form(CIFB), Cascade of Integrators with Feedforward Form(CIFF), Cascade of Resonators with Feedback Form(CRFB), and Cascade of Resonators with Feedforward Form(CRFF), resonator type DSMs turn out to be more susceptible to the pattern noise than the integrator type. Noise transfer functions of the investigated topologies are also presented.