• Proceedings of the Korean Information Science Society Conference
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• 2007.06d
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• pp.440-444
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• 2007

센서 네트워크를 구성하는 각 노드는 AA형 건전지를 사용하여 2년 6개월 이상 동작하는 것을 목표로 하며, 따라서 저전력을 고려하여 설계되어야 한다. 본 논문에서는 저전력 센서 네트워크를 위한 분산 컴퓨팅 모델을 제안한다. 제안된 모델은 우선 센서 노드에서 처리를 위한 에너지 소비와 통신을 위한 에너지 소비의 크기를 분석한다. 그리고 처리 에너지 비용을 지불하여 통신 에너지 감소라는 이득을 얻을 수 있음을 보인다. 한편, 이 기법은 특정 센서 노드의 에너지를 집중적으로 소비할 수 있음을 보이고, 이를 해결할 수 있는 에너지 균형 분산 컴퓨팅 모델을 제안한다. 시뮬레이션 기반 실험 결과 제안된 모델이 전체적인 에너지 소비를 낮추었을 뿐 아니라 센서 노드들 간에 에너지 균형도 이루고 있음을 알 수 있었다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.1
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• pp.81-90
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• 2004

The state assignment for a finite state machine greatly affects the delay, area, power dissipation, and testabilities of the sequential circuits. In order to improve the testabilities and power consumption, a new state assignment technique . based on m-block partition is introduced in this paper. By the m-block partition algorithm, the dependencies among groups of state variables are minimized and switching activity is further reduced by assigning the codes of the states in the same group considering the state transition probability among the states. In the sequel the length and number of feedback cycles are reduced with minimal switching activity on state variables. It is inherently contradictory problem to optimize the testability and power consumption simultaneously, however our new state assignment technique is able to achieve high fault coverage with less number of scan nfp flops by reducing the number of feedback cycles while the power consumption is kept low upon the low switching activities among state variables. Experiment shows drastic improvement in testabilities and power dissipation for benchmark circuits.

• The Journal of the Korea institute of electronic communication sciences
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• v.2 no.3
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• pp.163-167
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• 2007

In this paper, to design 8 bit RISC Microprocessor, a method of Clock Gating to reduce electric power consumption is proposed. In order to examine the priority, the comparison results of between a 8 bit Microprocessor which is not considered Low Power consumption and which is considered Low Power consumption using a methods of Clock Gating are represented. Within the a few periods, the results of comparing with a Microprocessor not considered the utilization of Clock Gating shows that the reduction of dynamic dissipation is minimized up to 21.56%.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.7
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• pp.38-44
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• 2008

In this paper, we introduce an low complexity and low power IR-UWB (impulse radio ultra wideband) baseband transceiver for wireless sensor network. The proposed baseband, implemented by TSMC 0.18um CMOS technology, has a simple structure in which a simplified packet structure and a digital synchronizer with 1-bit sampler to detect incoming pulses are used. Besides, clock gating method using gated clock cell as well as customized clock domain division can reduce the total power consumption drastically. As a result, the proposed baseband has about 23K digital gates with an internal memory of 2Kbytes and achieves about 1.8mW@1Mbps power consumption.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.451-454
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• 2015

This paper introduces 3 type of OTAs with $0.35-{\mu}m$ standard CMOS technology for Low-Power, Low-Voltage. The first type is a two-stage OTA designed to operate with a 1-V VDD and it has $1.774{\mu}W$ low power consumption. All transistors are operating in strong inversion. It takes Gm-Enhancement techniques to compensate gm, which is lowered by Bulk-Driven technique and has an Wide swing current mirror for low voltage operation and a Class-A output. The second type is a Two-stage OTA designed to operate with a 0.8-V VDD and It has 52nW low power consumption and 112dB high gain. The current mirror uses Composite Transistor binding Gates of two MOSFET to raise Rout which is similar with cascode structure. The third type is a Two-stage OTA designed to operate with a 0.6-V VDD and It has 160nW low power consumption and 72dB high gain. It takes Level Shift technique by Common Gate structure to amplify signals without additional bias voltage at second stage.

• The KIPS Transactions:PartA
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• v.13A no.3 s.100
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• pp.191-198
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• 2006

Today's portable electric consumer devices, which are operated by battery, tend to integrate more multimedia processing capabilities. In the multimedia processing devices, multimedia system-on-chips can handle specific algorithms which need intensive processing capabilities and significant power consumption. As a result, the power-efficiency of multimedia processing devices becomes important increasingly. In this paper, we propose a reconfigurable data caching architecture, in which data allocation is constrained by software support, and evaluate its performance and power efficiency. Comparing with conventional cache architectures, power consumption can be reduced significantly, while miss rate of the proposed architecture is very similar to that of the conventional caches. The reduction of power consumption for the reconfigurable data cache architecture shows 33.2%, 53.3%, and 70.4%, when compared with direct-mapped, 2-way, and 4-way caches respectively.

• The KIPS Transactions:PartA
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• v.14A no.3 s.107
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• pp.147-150
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• 2007

This paper describes a new low-swing inverter for low power consumption. To reduce a power consumption, an output voltage swing is in the range from 0 to VDD-2VTH. This can be done by the inverter structure that allow a full swing or a swing on its input terminal without leakage current. Using this low-swing voltage technology, we proposed a low-power 16$\times$16 bit parallel multiplier. The proposed circuits are designed with Samsung 0.35$\mu$m standard CMOS process at a 3.3V supply voltage. The validity and effectiveness are verified through the HSPICE simulation.. Compared to the previous works, this circuit can reduce the power consumption rate of 17.3% and the power-delay product of 16.5%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.89-95
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• 2008

In this paper, we designed a low power face detection hardware and analysed its power consumption. The face detection hardware was fabricated using Samsung 0.18um CMOS technology and it can detect multiple face locations from a 2-D image. The hardware is composed of 6 functional modules and 11 internal memories. We introduced two operating modes(SLEEP and ACTIVE) to save power and a clock gating technique was used at two different levels: modules and registers. In additional, we divided an internal memory into several pieces to reduce the energy consumed when accessing memories, and fully utilized low power design option provided in Synopsis Design Compiler. As a result, we could obtain 68% power reduction in ACTIVE mode compared to the original design in which none of the above low power techniques were used.

• Proceedings of the Korean Information Science Society Conference
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• 2003.04d
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• pp.274-276
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• 2003

센서 기술과 통신 기술의 발달로 센서 네트워크에 대한 연구가 활발히 진행되고 있다. 센서 노드는 주변환경을 관찰하고 그 결과를 센서 노드로 이루어진 네트워크를 통하여 사용자에게 전달한다. 센서 네트워크는 특정 기반 구조 없이 수행되어야 하기 때문에 데이터의 전달이 애드혹 네트워크에서의 라우팅 기법과 비슷하다. 하지만 센서 노드는 배터리 전력량에 의하여 수명이 결정되기 때문에 전력 소비를 줄이는 것이 매우 중요한 문제이다. 본 논문에서는 센서 노드의 위치에 따라 통신 상태를 유휴(idle) 상태에서 정지(sleep)상태로 변경하는 방법으로 전력 소비를 줄이는 MAC 프로토콜을 제안한다.

• Proceedings of the KIPE Conference
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• 2010.07a
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• pp.41-42
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• 2010

본 논문에서는 대면적 플라즈마 사인 보드 제어를 위한 저소비 전력용 인버터를 개발하였다. 이 인버터는 215*86mm 사이즈로 인가전압 220V, 출력전압 1200V, 스위칭 주파수 20KHz, 소비전력 50W 급인 인버터를 역률개선회로 PFC(Power Factor Correction)를 적용하여 리플을 줄이고 안정적인 전압 공급, 전체 전류 정격감소, 회생전압 상승분 억제, 유니버설 입력범위에서 동작 가능하게 만들었다. 고전압트랜스를 4개를 집적화 하였으며 전력 소비 전류가 감소되면서 온도가 상승되는 것을 막을 수 있었고 전자파도 줄일 수 있음을 보였다.