• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.5
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• pp.87-97
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• 2016

This work proposes a time-shared 10b DAC based on a two-step resistor string to minimize the effective area of a DAC channel for driving each AMOLED display column. The proposed DAC shows a lower effective DAC area per unit column driver and a faster conversion speed than the conventional DACs by employing a time-shared DEMUX and a ROM-based two-step decoder of 6b and 4b in the first and second resistor string. In the second-stage 4b floating resistor string, a simple current source rather than a unity-gain buffer decreases the loading effect and chip area of a DAC channel and eliminates offset mismatch between channels caused by buffer amplifiers. The proposed 1-to-24 DEMUX enables a single DAC channel to drive 24 columns sequentially with a single-phase clock and a 5b binary counter. A 0.9pF sampling capacitor and a small-sized source follower in the input stage of each column-driving buffer amplifier decrease the effect due to channel charge injection and improve the output settling accuracy of the buffer amplifier while using the top-plate sampling scheme in the proposed DAC. The proposed DAC in a $0.18{\mu}m$ CMOS shows a signal settling time of 62.5ns during code transitions from '$000_{16}$' to '$3FF_{16}$'. The prototype DAC occupies a unit channel area of $0.058mm^2$ and an effective unit channel area of $0.002mm^2$ while consuming 6.08mW with analog and digital power supplies of 3.3V and 1.8V, respectively.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.5
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• pp.67-74
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• 2013

A low-power 12-bit resistor string DAC for wireless sensor applications is presented. Two-step approach reduces complexity, minimizes power consumption and area, and increases speed. This chip is fabricated in 0.18-${\mu}m$ CMOS and the die area is $0.76mm{\times}0.56mm$. The measured power consumption is 1.8mW from the supply voltage of 1.8V. Measured SFDR(Spurious-Free Dynamic Range) is 70dB when the sampling frequency is less than 1 MHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.225-228
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• 2012

In this paper, a 10-bit digital-to-analog converter (DAC) with small area is proposed. The 10-bit DAC consists of a 8-bit decoder, a 2-bit time-interpolator, and a buffer amplifier. The proposed time-interpolation is achieved by controlling the charging time through a low-pass filter composed of a resistor and a capacitor. To implement the accurate time-interpolator, a control pulse generator using a replica circuit is proposed to minimize the effect of the process variation. The proposed 10-bit Time-Interpolation DAC occupies 61 % of the conventional 10-bit resistor-string DAC. The proposed DAC is designed using a $0.35{\mu}m$ CMOS process with a 3.3 V supply. The simulated DNL and INL are +0.15/-0.21 LSB and +0.15/-0.16 LSB, respectively.