• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.3
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• pp.82-88
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• 2014

We study the effect of mesh reordering on Laplacian smoothing for parallel high performance computing systems. Specifically, we use the Reverse-Cuthill McKee algorithm to reorder meshes and use Laplacian Smoothing to improve the mesh quality on Nonuniform memory access architecture-based parallel high performance computing systems. First, we investigate the effect of using mesh reordering on Laplacian smoothing for a single core system and extend the idea to NUMA-based high performance computing systems.

• KIISE Transactions on Computing Practices
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• v.20 no.12
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• pp.700-705
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• 2014

An anagram is a form of word play to find a new word from a set of given alphabet letters. Good human anagram solvers use the strategy of bigrams. They explore a constraint satisfaction network in parallel and answers consequently pop out quickly. In this paper, we propose a molecular computational algorithm using the same process as this. We encoded letters into DNA sequences and made bigrams and then words by connecting the letter sequences. From letters and bigrams, we performed DNA hybridization, ligation, gel electrophoresis and finally, extraction and separation to extract bigrams. From the matched bigrams and words, we performed the four molecular operations again to distinguish between right and wrong results. Experimental results show that our molecular computer can identify cor rect answers and incorrect answers. Our work shows a new possibility for modeling the cognitive and parallel thinking process of a human.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.6
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• pp.80-87
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• 2016

We propose a parallel mesh smoothing algorithm using graph coloring and OpenMP library for shared memory many core computer architectures. The proposed algorithm partitions a mesh into independent sets and performs a parallel mesh smoothing using OpenMP library. We study the effect of using various graph coloring and color reordering algorithms on the efficiency of performing the proposed parallel mesh smoothing algorithm. We also investigate the influence of using various OpenMP loop scheduling methods on the parallel mesh smoothing efficiency.

• KIISE Transactions on Computing Practices
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• v.20 no.12
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• pp.682-687
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• 2014

First phoneme queries are important functionalities that provide an improvement in the usability of interfaces that produce errors frequently due to their restricted input environment, such as in navigators and mobile devices. In this paper, we propose a time-space efficient data structure for Korean first phoneme queries that disassembles Korean strings in a phoneme-wise manner, rearranges them into circular strings, and finally, indexes them using the extended Burrows-Wheeler Transform. We also demonstrate that our proposed method can process more types of query using less space than previous methods. We also show it can improve the search time when the query length is shorter and the proportion of first phonemes is higher.

• The KIPS Transactions:PartA
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• v.12A no.5 s.95
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• pp.451-460
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• 2005

We present a methodology to design energy-efficient data paths using FPGAs. Our methodology integrates domain specific modeling, coarse-grained performance evaluation, design space exploration, and low-level simulation to understand the tradeoffs between energy, latency, and area. The domain specific modeling technique defines a high-level model by identifying various components and parameters specific to a domain that affect the system-wide energy dissipation. A domain is a family of architectures and corresponding algorithms for a given application kernel. The high-level model also consists of functions for estimating energy, latency, and area that facilitate tradeoff analysis. Design space exploration(DSE) analyzes the design space defined by the domain and selects a set of designs. Low-level simulations are used for accurate performance estimation for the designs selected by the DSE and also for final design selection We illustrate our methodology using a family of architectures and algorithms for matrix multiplication. The designs identified by our methodology demonstrate tradeoffs among energy, latency, and area. We compare our designs with a vendor specified matrix multiplication kernel to demonstrate the effectiveness of our methodology. To illustrate the effectiveness of our methodology, we used average power density(E/AT), energy/(area x latency), as themetric for comparison. For various problem sizes, designs obtained using our methodology are on average $25\%$ superior with respect to the E/AT performance metric, compared with the state-of-the-art designs by Xilinx. We also discuss the implementation of our methodology using the MILAN framework.