• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.5
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• pp.1-10
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• 1998

Satellite communication is getting more important in the coming 21st century because of its wide areas sevice capability, ease of access, and fast channel establishment. As such, satellite communication networks will be the basis of the global communication system in cooperation with the ground ATM networks. In this paper, we consider an efficient transmission methodology of ATM cells over the satellite communication channel. We first analyze possible bottlenecks and performance deterioration factors in the case, and then propose an enhanced cell trasmission mechanism. In order to use satellite channel for ATM cell transmission, the application of complicated channel coding is inevitable. However, the forwared error control such as convolutional encoding brings forth burst errors, which calls for the application of some kind of interleaving mechanism to randomize the burst errors at the receiver. Another aspect which should b econsidered in satellite communication system is the inherent transmission delay, which can be very considered in satellite communication system is te inherent transmission delay, which can be very critical to the delay-sensitive ATM traffic. Therefore, we propose that the processing delay at the block interleaving stage should be controlled propose a variable-size block interleaving mechanism which utilizes the predicted transmission delay for each traffic in the queues of the transmitter. According to the computer simulation, the proposed mechanism could improve the overall performance by drastically reducing the ATM cell drop rate owing to the excessive transmission delay.

• 한국정보통신설비학회:학술대회논문집
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• 2005.08a
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• pp.427-430
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• 2005

A multi-code biorthogonal code keying (MBCK) system consists of multiple waveform coding blocks, and the sum of output codewords is transmitted. Drawback of MBCK is that it requires amplifier with high linearity because its output symbol is multi-level. MBCK with constant amplitude precoding block (CA-MBCK) has been proposed, which guarantees sum of orthogonal codes to have constant amplitude. The precoding block in CA-MBCK is a redundant waveform coder whose input bits are generated by processing the information bits. Redundant bits of constant amplitude coded CA-MBCK are not only used to make constant amplitude signal but also used to improve the BER performance at the receiver. In this paper, we proposed a transmission scheme which combines CA-MBCK with $Q^2PSK$ modulation to improve bandwidth efficiency of CA-MBCK and also uses chip interleaving to maintain a constant amplitude feature of CA-MBCK. bandwidth efficiency of a proposed transmission scheme is increased fourfold. And the BER performance of the scheme is same as that of CA-MBCK.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.5
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• pp.1135-1140
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• 2011

This paper proposes a DTMB deinterleaver structure to reduce the SDRAM power consumption with buffer conversion and the single pointer-register structure. The DTMB deinterleaver with deep interleaving for higher performance consists of long delay buffers allocated on SDRAM. The conventional structure activates a new SDRAM row almost everytime when it reads and writes a datum. In the proposed structure, long buffers are transformed into several short buffers so that the number of row activations is reduced. The single pointer-register structure solves the problem of many pointer-registers. The experimental results show that the SDRAM power consumption can be reduced to around 37% with slight logic area reduction.

• Proceedings of the KIPE Conference
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• 2017.07a
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• pp.24-25
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• 2017

In this paper, a low cost bridgeless interleaved power factor correction topology for electric vehicle charger application is proposed. With the proposed topology the number of switches, inductors, current sensors and associated circuits can be reduced, thereby reducing the cost of the system as compared to the conventional bridgeless PFC circuit. The reduced input current ripple by the proposed interleaved topology makes it suitable for high power applications such as electric vehicle chargers since it can reduce the size of the inductor core and the Electro Magnetic Interference (EMI) problem. In the proposed topology only one current sensor is required. All the boost inductor currents can be reconstructed by sampling the output current and used to control the input current. Therefore the typical problem caused by the unequal current gain of each current sensor inherently does not exist in the proposed topology. In addition the current sharing between converters can be achieved more accurately and the high frequency distortion is decreased. The performance of the proposed converter is verified by the experimental results with a prototype of 6.6kW bridgeless interleaved PFC circuit.

• Proceedings of the Korea Information Processing Society Conference
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• 2000.04a
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• pp.654-658
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• 2000

고효율의 멀티미디어 통신 서비스를 제공하기 위해 오류정정 능력이 뛰어난 채널코딩 기법과 차세대 통신 시스템에서 영상서비스는 그 데이터 양의 방대함으로 인해 효과적인 영상 압축 기법이 요구되고 있다. 또한 디지털 영상물의 저작권 보호(copyright protection)에 대한 디지털 워터마킹 기술이 중요한 현안이 되고 있다. 본 논문에서는 멀티미디어 통신 시스템에서 고화질의 영상을 보장하기 위한 채널 코딩기법을 제안하고자 한다. 이를 위해 연집오류를 산발 오류로 분포시킬 수 있는 새로운 인터리빙 방법의 제안과 터보 코드를 적용하여 채널상에서 발생하는 잡음을 제거하는 방법을 제안하고자 한다

• The Transactions of the Korean Institute of Power Electronics
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• v.26 no.2
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• pp.96-105
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• 2021

Large-scale power converters consist of series or parallel module combinations. In these modular converter systems, the interleaving technique can be applied to improve capacitor reliability by reducing the ripple of the I/O current in which each module operates as a phase difference. However, when applying the interleaving technique for conventional three-level boost converters, the short-circuit period of the converter can be an obstacle. Such problem is caused by the absence of a low-level inductor of the conventional three-level boost converter. To solve this problem, a three-level boost converter with a low-level inductor is proposed and analyzed to enable interleaved operation. In the proposed circuit, the current ripple of the output capacitor depends on the neutral point connections between the modules. In this study, the ripple current is analyzed by the neutral point connections of the three-level boost converter that has a low-level inductor, and the effectiveness of the proposed circuit is proven by simulation and experiment.

• Proceedings of the KIPE Conference
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• 2016.11a
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• pp.67-68
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• 2016

본 논문에서는 높은 승 강압비를 갖는 비절연형 양방향 컨버터를 제안한다. 제안하는 양방향 컨버터는 입력-병렬/출력-직렬(Parallel-Input/Series-Output, PISO) 구조로 인터리빙효과와 높은 전압이득을 얻을 수 있고 소자들의 전압정격이 고전압측 전압의 1/4배 수준으로 소자 선정이 용이하다. 또한, PWM plus Phase-Shift(PPS) 제어기법을 적용하여 전력의 흐름을 제어하면서 소프트스위칭을 최적화할 수 있다. 2kW급 시작품을 통해 듀티(D) 0.51 ~ 0.64를 사용하여 7 ~ 10배의 승 강압비를 달성하였으며 최고효율 96.1% 96.1%, 정격부하에서 95.9%, 96.0%를 달성하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.8
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• pp.63-72
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• 2012

In this paper, we proposed a parallel architecture of line & block edge filter for high-performance H.264/AVC deblocking filter for Quad Full High Definition(Quad FHD) video real time processing. To improve throughput, we designed 4-parallel block edge filter with 16 line edge filter. To reduce internal buffer size and processing cycle, we scheduled 4-parallel zig-zag scan order as deblocking filtering order. To avoid data conflicts we placed 1 delay cycle between block edge filtering. We implemented interleaving buffer, as internal buffer of block edge filter, to sharing buffer for reducing buffer size. The proposed architecture was simulated in 0.18um standard cell library. The maximum operation frequency is 108MHz. The gate count is 140.16Kgates. The proposed H.264/AVC deblocking filter can support Quad FHD at 113.17 frames per second by running at 90MHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39C no.2
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• pp.199-208
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• 2014

Code division multiple access (CDMA) is one of the promising medium access control (MAC) schemes for underwater acoustic sensor networks because of its robustness against frequency-selective fading and high frequency-reuse efficiency. As a way of performance evaluation, sea or lake experiment has been employed along with computer simulation.. In this study, we design the underwater CDMA forward-link transceiver and evaluate the feasibility aginst harsh underwater acoustic channel in water-tank first. Then, based on the water-tank experiment results, we improved the transceiver and showed the improvements in a lake experiment. A pseudo random noise code acquisition process is added for phase error correction before decoding the user data by means of a Walsh code in the receiver. Interleaving and convolutional channel coding scheme are also used for performance improvement. Experimental results show that the multiplexed data is recovered by means of demultiplexing at receivers with error-free in case of two users while with less than 15% bit error rate in case of three and four users.

• Journal of KIISE:Computing Practices and Letters
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• v.14 no.2
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• pp.201-205
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• 2008

The flash memory is widely used as a main storage of embedded devices. It is adopted as a storage of database as growing the capacity of the flash memory. We run TPC-C benchmark on various FTL algorithms. But, the database shows poor performance on flash memory because the characteristic of I/O requests is full random. In this paper, we show the performance of all existing FTL algorithms is very poor. Especially, the FTL algorithm known as good at small mobile equipment shows worst performance. In addition, the chip-inter leaving which is a technique to improve the performance of the flash memory doesn't work well. In this paper, we inform you the reason that we need a new FTL algorithm and the direction for the database in the future.