• Journal of Broadcast Engineering
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• v.15 no.1
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• pp.29-39
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• 2010

This paper presents and analyzes laboratory test results of distributed translator (DTxR) for distributed frequency network (DFN) in the ATSC (Advanced Television Systems Committee) terrestrial digital TV broadcasting system. The DTxR laboratory test is classified to receiving part test and transmitting part test. The receiving part test includes dynamic range, random noise, single echo, and adjacent channel interference. The transmitting part test includes quality of output signal (out-of channel emission, quality of transmitting signal, and phase noise), frequency synchronization among output signals, and TxID (Transmitter Identification) signal's affect to the legacy receiver. By the laboratory test results, the receiving part of DTxR eliminates average -2.5 dB of single echo and has average 17.5 dB at TOV (Threshold of Visibility) under random noise environment. In addition, the transmitting part of DTxR satisfies the specification of US FCC (Federal Communications Commission), and frequency difference among DTxR output signals is less than 0.001 Hz.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.3
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• pp.46-55
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• 2016

This work proposes a 13b 100MS/s 45nm CMOS ADC with a high dynamic performance for IF-domain high-speed signal processing systems based on a four-step pipeline architecture to optimize operating specifications. The SHA employs a wideband high-speed sampling network properly to process high-frequency input signals exceeding a sampling frequency. The SHA and MDACs adopt a two-stage amplifier with a gain-boosting technique to obtain the required high DC gain and the wide signal-swing range, while the amplifier and bias circuits use the same unit-size devices repeatedly to minimize device mismatch. Furthermore, a separate analog power supply voltage for on-chip current and voltage references minimizes performance degradation caused by the undesired noise and interference from adjacent functional blocks during high-speed operation. The proposed ADC occupies an active die area of $0.70mm^2$, based on various process-insensitive layout techniques to minimize the physical process imperfection effects. The prototype ADC in a 45nm CMOS demonstrates a measured DNL and INL within 0.77LSB and 1.57LSB, with a maximum SNDR and SFDR of 64.2dB and 78.4dB at 100MS/s, respectively. The ADC is implemented with long-channel devices rather than minimum channel-length devices available in this CMOS technology to process a wide input range of $2.0V_{PP}$ for the required system and to obtain a high dynamic performance at IF-domain input signal bands. The ADC consumes 425.0mW with a single analog voltage of 2.5V and two digital voltages of 2.5V and 1.1V.