• Journal of Biomedical Engineering Research
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• v.16 no.4
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• pp.507-516
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• 1995

The nonstationary identifier in the DCT domain is suggested in this study for the identification of AR parameters of above-lesion upper-trunk electromyographic (EMG) signals as a means of developing a reliable real time signal to control functional electrical stimulation (FES) in paraplegics to enable primitive walking. As paraplegic shifts his posture from one attitude to another, there is transition period where the signal is clearly nonstationary. Also as muscle fatigues, nonstationarities become more prevalent even during stable postures. So, it requires a develpment of time varying nonstationary EMG signal identifier. In this paper, time varying nonstationary EMG signals are transformed into DCT domain and the transformed EMG signals are modeled and analyzed in the transform domain. In the DCT domain, we verified reduction of condition number and increment of the smallest eigenvalue of input correlation matrix that influences numerical properties and mean square error were compared with SLS algorithm, and the proposed algorithm is implemented using IMS T-805 parallel processing computer for real time application.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.50 no.6
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• pp.385-391
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• 2022

This paper presents to develop a path planning algorithm combining gradient descent-based path planning (GBPP) and particle swarm optimization (PSO) for considering prohibited flight areas, terrain information, and characteristics of fixed-wing unmmaned aerial vehicle (UAV) in 3D space. Path can be generated fast using GBPP, but it is often happened that an unsafe path can be generated by converging to a local minimum depending on the initial path. Bio-inspired swarm intelligence algorithms, such as Genetic algorithm (GA) and PSO, can avoid the local minima problem by sampling several paths. However, if the number of optimal variable increases due to an increase in the number of UAVs and waypoints, it requires heavy computation time and efforts due to increasing the number of particles accordingly. To solve the disadvantages of the two algorithms, hierarchical path planning algorithm associated with hierarchical particle swarm optimization (HPSO) is developed by defining the initial path, which is the input of GBPP, as two variables including particles variables. Feasibility of the proposed algorithm is verified by software-in-the-loop simulation (SILS) of flight control computer (FCC) for UAVs.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.4 s.334
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• pp.19-28
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• 2005

In this paper, we proposed a parallel fast 2-D discrete wavelet transform hardware architecture based on lifting scheme. The proposed architecture improved the 2-D processing speed, and reduced internal memory buffer size. The previous lifting scheme based parallel 2-D wavelet transform architectures were consisted with row direction and column direction modules, which were pair of prediction and update filter module. In 2-D wavelet transform, column direction processing used the row direction results, which were not generated in column direction order but in row direction order, so most hardware architecture need internal buffer memory. The proposed architecture focused on the reducing of the internal memory buffer size and the total calculation time. Reducing the total calculation time, we proposed a 4-way data flow scheduling and memory based parallel hardware architecture. The 4-way data flow scheduling can increase the row direction parallel performance, and reduced the initial latency of starting of the row direction calculation. In this hardware architecture, the internal buffer memory didn't used to store the results of the row direction calculation, while it contained intermediate values of column direction calculation. This method is very effective in column direction processing, because the input data of column direction were not generated in column direction order The proposed architecture was implemented with VHDL and Altera Stratix device. The implementation results showed overall calculation time reduced from $N^2/2+\alpha$ to $N^2/4+\beta$, and internal buffer memory size reduced by around $50\%$ of previous works.