Analysis of Drain Induced Barrier Lowering of Asymmetric Double Gate MOSFET for Channel Doping Profile (비대칭 DGMOSFET의 채널도핑분포함수에 따른 드레인 유도 장벽 감소현상 분석)
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- Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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- 2015.10a
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- pp.863-865
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- 2015