• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.8
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• pp.56-63
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• 2010

This work proposes a 12b 100MS/s 0.13um CMOS pipeline ADC for battery-powered mobile video applications such as DVB-Handheld (DVB-H), DVB-Terrestrial (DVB-T), Satellite DMB (SDMB), and Terrestrial DMB (TDMB) requiring high resolution, low power, and small size at high speed. The proposed ADC employs a three-step pipeline architecture to optimize power consumption and chip area at the target resolution and sampling rate. A single shared and switched op-amp for two MDACs removes a memory effect and a switching time delay, resulting in a fast signal settling. A two-step reference selection scheme for the last-stage 6b FLASH ADC reduces power consumption and chip area by 50%. The prototype ADC in a 0.13um 1P7M CMOS technology demonstrates a measured DNL and INL within 0.40LSB and 1.79LSB, respectively. The ADC shows a maximum SNDR of 60.0dB and a maximum SFDR of 72.4dB at 100MS/s, respectively. The ADC with an active die area of 0.92 $mm^2$ consumes 24mW at 1.0V and 100MS/s. The FOM, power/($f_s{\times}2^{ENOB}$), of 0.29pJ/conv. is the lowest of ever reported 12b 100MS/s ADCs.