• Proceedings of the KIEE Conference
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• 2015.07a
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• pp.1064-1065
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• 2015

단상 계통 연계형 전력 변환기에서 계통과 연계하기 위해서는 계통의 위상 정보를 정확히 측정하여 전력 변환기의 출력 주파수와 위상이 동일한 상태로 전류가 공급 되도록 해야 한다. 본 논문에서는 단상 d-q 좌표 변환 기법을 통한 위상 동기화 기법을 적용하여 왜곡된 계통전압이 d축 전압에 야기 되는 에러 성분을 최소화 하는 보상 기법을 제안한다. 제안된 기법은 동기 d축 전압을 일정한 주기로 적분하여 에러 성분을 최소화 한 후, PI제어를 통해 d축 전압을 0으로 수렴하게 하는 기법이다. 제안된 기법은 추가적인 하드웨어를 요구하지 않는다. 본 논문의 타당성을 검증하기 위해 3[kW]급 단상 계통 연계형 전력변환기 시작품을 제작하고 실험을 통해 증명하였다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.8
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• pp.1188-1195
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• 2022

The 6-port phase correlator consists of one in-phase power divider and three 3-dB 90-degree phase difference power dividers, and is mainly used in a demodulation circuit that determines the phase of an input signal. This paper proposes the wideband 6-port phase correlator that consists of an in-phase power divider using a wideband 2:1 impedance transformer with three 37.5-Ω coaxial cables, and a 3-dB 90-degree phase difference power divide using Wireline. The proposed wideband phase correlator fabricated at a center frequency of 1000MHz has the value of the input reflection coefficient(S₁₁ and S₂₂) -14dB or less in the frequency range of 640~1270MHz. Also, the signal transmission characteristic(S_i1), from the in-phase power divider input port to four output ports, has the amplitude of -6.5±0.6dB and the phase error of within ±3.4°, and the signal transmission characteristic(S_i2), from the 90 degree phase difference power divider input port to four output ports, has the amplitude of -6.1±0.6dB and the phase error of within ±6.2°.

• Journal of Satellite, Information and Communications
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• v.12 no.2
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• pp.61-64
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• 2017

A phase shifter is one of the key components that change the phase of an individual antenna in millimeter-wave phased array system. This paper presents a low-loss phase shifter design with two parallel 2-state amplifiers. To get the same gain of $0^{\circ}/180^{\circ}$ each state, delay lines are in the middle of each stage of the 2-Stage amplifiers. Normally, when adding AMPs in parallel, a power combiner/divider such as Wilkinson Power Combiner/Divider is added, but they are directly connected because it can cause added losses in silicon wafer. The measured data shows 12dB gain and 174-degree phase difference at 5GHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.4C
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• pp.380-387
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• 2002

In this paper, the effect of the phase noise of a local oscillator on the ACPR of a transmitter and the reception sensitivity of a receiver to meet the TIA/EIA/IS-98-D for the CDMA mobile station was analyzed. And the optimum condition for performance of the local oscillator was suggested. It was found that the phase noise level of the local oscillator in a receiver and a transmitter should be below -138.3dBc/Hz and -120dBc/Hz, respectively, at 900kHz offset. It was confirmed that the reception sensitivity and ACPR efficiency were satisfactory when the signal of the local oscillator to the down-converter of a receiver with the phase noise level of less than -138.3dBc/Hz is supplied to the up-converter of the transmitter.

• Journal of IKEEE
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• v.25 no.3
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• pp.517-527
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• 2021

This paper presents the phase-shift full-bridge DC-DC converter using the one-chip micom. The proposed converter primary is the full-bridge power topology that operates with the unipolar pulse-width modulation (PWM) by the phase-shift method, and the secondary is the full-bridge full-wave rectifier composed of four diodes. The control of proposed converter is performed by the one-chip micom and its MOSFET switches are driven by the bootstrap circuit. Thus the total system of proposed converter is simple. The proposed converter achieves high-efficiency using the resonant circuit and blocking capacitor. In this paper, first, the power-circuit operation of proposed converter is explained according to each operation mode. And the power-circuit design method of proposed converter is shown, and the software control algorithm on the micom and the feedback and switch drive circuits operating the proposed converter are described, briefly. Then, the operation characteristics of proposed converter are validated through the experimental results of a designed and implemented prototype converter by the shown design and implementation method in this paper. The highest efficiency in the results was about 92%.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.1 s.116
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• pp.15-23
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• 2007

A simple six-port direct conversion QPSK receiver which is made up of a six-port phase correlator, a signal power detector, and I/Q channel signal de-modulator is designed and implemented in this paper. The output phase signals of six-port phase correlator are also analysed. On the basis of $90^{\circ}C$ phase relation among the six-port phase correlator output signals, the QPSK de-modulation circuit is designed by a simple circuit. The six-port phase correlator is made up of $90^{\circ}$ hybrid branch line and power detector. The six-port phase correlator, which is designed in frequency range of 11.7 to 12.0 GHz, gets the phase error characteristics less than $5^{\circ}$. By considering matching network and amplitude balance in the designed fiequency range, the designed six-port direct conversion QPSK receiver demodulates the I and Q signals with performance less than $5^{\circ}$ phase error.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.10a
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• pp.242-245
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• 2001

본 논문은 디지털 위성용 하향변환기에 적용되는 고안정 전압제어 마이크로파 발진기의 위상잡음 특성을 분석하였다. 전압제어 마이크로파 발진기는 능동소자의 비선형 등가모델과 궤환회로의 영향을 고려하여 유전체 공진 마이크로파 발진기를 위상잡음과 출력 전력에 절충(trade-off)하여 설계하였고, 13.25GHz의 발진주파수에서 출력이득은 12dBm이고, 위상잡음은 옵셋 주파수 100KHz 에서 -107.91dBc를 보였다. 바렉터 다이오드 동작에 의한 튜닝 범위는 2MHz/V로 위상동기 발진기에 응용할 수 있음을 보였다.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.14 no.1
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• pp.37-42
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• 2021

This paper presents a jitter and phase noise characteristic improved phase-locked loop (PLL) with loop filter voltage detector(LFVD) and frequency voltage converter(FVC). Loop filter output voltage variation is determined through a circuit made of resistor and capacitor. The output signal of a small RC time constant circuit is almost the same as to loop filter output voltage. The output signal of a large RC time constant circuit is the average value of loop filter output voltage and becomes a reference voltage to the added LFVD. The LFVD output controls the current magnitude of sub-charge pump. When the loop filter output voltage increases, LFVD decreases the loop filter output voltage. When the loop filter output voltage decreases, LFVD increases the loop filter output voltage. In addition, FVC also improves the phase noise characteristic by reducing the loop filter output voltage variation. The proposed PLL with LFVD and FVC is designed in a 0.18um CMOS process with 1.8V power voltage. Simulation results show 0.854ps jitter and 30㎲ locking time.

• Korean Journal of Optics and Photonics
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• v.15 no.3
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• pp.274-277
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• 2004

An integrated photonic radio frequency (RF) phase shifter has been proposed and fabricated using a nested dual Mach-Zehnder modulator configuration in a new electro-optic polymer. The fabricated device shows a continuous voltage control of the RF signal phase. A near-linear phase shift exceeding 108$^{\circ}$was obtained for a 16-GHz microwave signal by tuning the do control voltage over a 7.8- $V_{pp}$ range.e.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.5
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• pp.677-684
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• 2021

This paper presents a time-to-digital converter for measuring absolute time differences. The time-to-digital converter was designed and fabricated in 0.18-um CMOS technology and it can be applied to Light Detection and Ranging system which requires long time-cover range and 50ps time resolution. Since designed time-to-digital converter adopted the reference clock of 625MHz generated by phase locked loop, it could have absolute time resolution of 50ps after automatic calibration and its cover range was over than 800ns. The time-to-digital converter adopted a counter and chain delay lines for time measurement. The counter is used for coarse time measurement and chain delay lines are used for fine time measurement. From many times experiments, fabricated time-to-digital converter has 50 ps time resolution with maximum INL of 0.8 LSB and its power consumption is about 70 mW.