• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.2
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• pp.122-133
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• 2013

An arbiter-based simple phase decision circuit (PDC) optimized for high-resolution phase-to-digital converter made up of an analog phase-frequency detector and a time-to-digital converter for all-digital phase-locked loops is proposed. It can distinguish very small phase difference between two pulses even though it consumes lower power and has smaller input-to-output delay than the previously reported PDC. Proposed PDC is realized using 130-nm CMOS process and demonstrated by transistor-level simulations. A 5-bit P2D having no offset nor deadzone using the PDC is also demonstrated. A harmonic-lock-free and small-phase-offset delay-locked loop for fixing the P2D resolution regardless of PVT variations is also proposed and demonstrated.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.11
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• pp.31-37
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• 1998

Magnitude/phase controlling circuit which is composed of attenuator and phase shifter make phase/gain cross-coupling, so too much tuning time is needed to find optimum operation point. In this paper, vector attenuator which control magnitude and phase of input signals is proposed. Vector attenuator in past ignores phase variation characteristics of attenuator, but vector attenuator of this paper compensates phase variation characteristics of attenuator. This vector attenuator consists of 0$^{\circ}$/180$^{\circ}$ phase shifter and low phase shifting attenuator and so forth. A 0$^{\circ}$/180$^{\circ}$ phase shifter has 0$^{\circ}$/179.9$^{\circ}$ phase shifting characteristics at a center frequency 881 MHz and a low phase shifting attenuator has an attenuation of 25dB, within the limit of 3.6$^{\circ}$ phase shift and less than -20dB reflection characteristics at both input and output ports. The designed vector attenuator shows that cartesian coordinate plane of output signal space can be represented correctly.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.12
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• pp.2716-2724
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• 2012

In this paper, a Phase Difference-to-Voltage Converter (PDVC) has been introduced into a conventional fractional-N PLL to suppress fractional spurs. The PDVC controls charge pump current depending on the phase difference of two input signals to phase frequency detector. The charge pump current decreases as the phase difference of two input signals increase. It results in the reduction of fractional spurs in the proposed fractional-N PLL. The proposed fractional-N PLL with PDVC has been designed based on a 1.8V $0.18{\mu}m$ CMOS process and proved by HSPICE simulation.

• Journal of IKEEE
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• v.16 no.4
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• pp.322-327
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• 2012

In this paper, a digital phase-locked loop(Digital-PLL) circuit with a new phase-to-digital converter(P2D) is described. The proposed digital PLL is composed a P2D, a digital loop filter(DLF), and a digitally controlled oscillator(DCO). The P2D generates a digital code for a phase error. The proposed P2D used a binary phase frequency detector(BPFD) and a counter in place of a time-to-digital converter(TDC) for simple structure, compact area and low power consumption. The proposed circuit was designed with CMOS 0.18um process. The simulation shows the circuit operates with the 1.0 to 2.2GHz with the power consumption of 16.2mW at 1.65GHz and the circuit occupies the chip area of $0.096mm^2$.

• The Journal of the Acoustical Society of Korea
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• v.5 no.4
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• pp.37-45
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• 1986

초음파 Hyperthermia를 이용한 치료는 정상세포에 열적 손상을 주지 않으면서 종양 부위만을 적당한 온도로 가열하여야 하며 따라서 종양세포와 정상세포에 대한 정확한 초음파 세기조절이 필요하 게 된다. 본 논문에서는 초음파 Hyperthermia 용 변환기로서 초점거리와 가열범위를 전자적으로 쉽게 조절할 수 있는 동심환 배열 변환기를 설계하였으며 컴퓨터 모의 실험을 통해 그 성능을 예측하였다. 설계된 변환기는 유효직경 118mm, 동작주파수 320kHz 이며 배열 요소의 수는 12개이다. 그리고 이와 같은 동심환 변환기를 동작시키기 위해 카운터를 이용한 디지털 위상 조절 회로를 설계 제작하였으며, 실험 결과, 위상차를 갖는 신호를 발생시킬 수 있었다.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.46 no.3
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• pp.251-256
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• 2018

In the case of a radar repeater that used for the trajectory tracking of a high-speed aircraft, it emits pulses of short width. For phase displacement of these signals a branch type phase shifter is used. The phase on the transmission line is changed by utilizing the variable reactance at the end of the displacement branch transmission line. Further, it is easy to control the high output signal, and there is an advantage that the insertion loss is not large even when the reactance fails. In this paper, we will discuss the fabrication test results of a 400 W class phase shifter that sequentially displaces the phase at $0^{\circ}$, $30^{\circ}$, $60^{\circ}$, $90^{\circ}$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.7
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• pp.1180-1186
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• 2008

The LNB phase noise of user terminal for high data rate satellite transmission was analyzed in this paper. The phase noise severely affects the service performance in low data rate transmission as well as multi-mode signal for high data rate. As the satellite link frequency is increased, the effects of phase noise for multi-mode signal is increased. The phase noise of LNB, which is operated in high frequency band, is about equal to the transmission system phase noise and have an major effects on service performance degradation. The available transmission mode was analyzed in presence of phase noise of LNB and analysis method for LNB phase noise spectrum distribution was proposed in multi-mode signal.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.13 no.7
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• pp.649-656
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• 2002

This paper addresses the phase noise analysis of high-speed DH-PLL(Digital Hybrid Phase-Locked Loops) frequency synthesizer. Because of the additional quantization noise of D/A converter in DH-PLL, the phase noise of DH-PLL is increased than the conventional PLL. Three kinds of noise sources such as reference input, D/A converter, and VCO(Voltage Controlled Oscillator) are considered to analyze the phase noise. It largely depends on the closed loop bandwidth and frequency synthesis division ratio(N) so that we can decide the optimal closed loop bandwidth to minimize the phase noise of DH-PLL. It is shown that the simulation results closely match with the results of analytical approach.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.5
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• pp.1071-1077
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• 2010

The six-port phase correlator using lumped elements was designed and fabricated in this paper, also the receiving performance of L-band direct conversion receiver using lumped six-port phase correlator element was analyzed. The proposed L-band lumped six-port phase correlator element was composed of a resistive power divider and the twist-wire coaxial cables. The proposed lumped six-port structure provides the small-sized configuration and wide-band characteristics. The performance of the L-band lumped direct conversion receiver structure was measured under the conditions of 1.69 GHz frequency for LO-CW signal and RF-QPSK signal, which are input signals for the lumped six-port phase correlator element. The direct conversion receiving structure using the proposed lumped six-port phase correlator element can recovered the good digital I/Q signal.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.6
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• pp.63-70
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• 2014

A low-N phase-locked loop clock generator with frequency multiplier is proposed to improve phase noise characteristic. Delay-variance voltage converter (DVVC) generates output voltages according to the delay variance of delay stages in voltage controlled oscillator. The output voltages of average circuit with the output voltages of DVVC are applied to the delay stages in VCO to reduce jitter. The HSPICE simulation of the proposed phase-locked loop clock generator with a $0.18{\mu}m$ CMOS process shows an 11.3 ps of peak-to-peak jitter.