• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 2002.11a
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• pp.88-91
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• 2002

자기 수축 발생기(self-shrinking generator)는 Meier와 Staffelbach에 의해 제안되었으며[4], 구조가 간단하고 키수열을 생성하는 속도가 빠르기 때문에 스트림 암호시스템으로 각광받고 있다 [5]. 본 논문에서는 자기 수축 발생기의 새로운 구성방법을 제안한다. 제안된 자기 수축 발생기는 하나의 선형귀환회로와 주어진 짝수 m에 의하여 정의되며 일반적으로 선형귀환회로의 귀환다항식으로 원시다항식을 사용한다. 이 경우 키수열은 균형성을 만족하며, 선형귀환회로의 귀환다항식의 차수를 $d_{Y}$ 라고 하면 주기는 $d_{Y-2}$ 이다. m을 $2^{η}$ζ로 표현하면 선형복잡도 Lz는 $d_{Y}$ ＋η-3/$\leq$ $L_{Z}$ $\leq$m/2($d_{Y}$ -1 - ($d_{Y}$ -2))이다. 따라서 제안된 자기 수축 발생기는 기존의 자기 수축 발생기에 비하여 암호학적으로 우수한 성질을 갖는다.다.

• The Journal of the Korea institute of electronic communication sciences
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• v.13 no.1
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• pp.133-140
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• 2018

In this paper we discover the generation principle of a sequence when the characteristic polynomial of the sequence is a power of a primitive polynomial. With the generation principle, we can rearrange a sequence. Also we get the linear complexity and the required term of the sequence efficiently.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.14 no.6
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• pp.590-603
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• 1989

In tnis paper, the CRC-CCITT code and primitive polynomial CRC code are selected for analysing error detecting performance. However, general formulas for obtaining the weight distribution of these two CRC codes are not so far dericed. So, a new method for calculating the weight distribution of the shortened cyclic Hamming code is presented and an undetected error probability of these two codes is obtained when used in cell of ATM for broadband ISDN user-network interface. Consequently, we show that CRC code too much does affect its error detection performance. All the computer simulation is performed by IBM PC/AT.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.4
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• pp.81-87
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• 1989

A cellular array multiplier for performing the multiplication of two elements in the finite field GF($2^m$) is presented in this paper. This multiplier is consisted of three operation part ; the multiplicative operation part, the modular operation part, and the primitive irreducible polynomial operation part. The multiplicative operation part and the modular operation part are composed by the basic cellular arrays designed AND gate and XOR gate. The primitive iirreducible operation part is constructed by XOR gates, D flip-flop circuits and a inverter. The multiplier presented here, is simple and regular for the wire routing and possesses the properties of concurrency and modularity. Also, it is expansible for the multiplication of two elements in the finite field increasing the degree m and suitable for VLSI implementation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.6A
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• pp.405-413
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• 2003

This paper presents new DSP (Digital Signal Processor) instructions and their hardware architecture to efficiently implement RS (Reed-Solomon) codecs, which is one of the most widely used FEC (Forward Error Control) algorithms. The proposed DSP architecture can implement various primitive polynomials by program, and thus, hardwired codecs can be replaced. The new instructions and their hardware architecture perform GF (Galois Field) operations using the proposed GF multiplier and adder. Therefore, the proposed DSP architecture can significantly reduce the number of clock cycles compared with existing DSP chips. It can perform RS decoding rate of up to 228.1 Mbps on 130MHz DSP chips.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.14 no.6
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• pp.25-30
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• 2004

Linear cellular automata(CA) which generate maximum-length cycles, have wide applications in generation of pseudo-random patterns, signature analysis, cryptography and error correcting codes etc. Linear CA whose characteristic polynomial is primitive has been studied. In this paper Ive propose a effective method for generation of a variety of maximum-length CA(MLCA). And we show that the complemented CA's derived from a linear MLCA are all MLCA. Also we analyze the Properties of complemented MLCA. And we prove that the number of n-cell MLCA is ${\phi}(2^{n}-1)2^{n+1}$/n.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.38 no.1
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• pp.27-34
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• 2001

The multiplication algorithm using the primitive irreducible trinomial $x^m+x+1$ over $GF(2^m)$ was proposed by Mastrovito. The multiplier proposed in this paper consisted of the multiplicative operation unit, the primitive irreducible operation unit and mod operation unit. Among three units mentioned above, the Primitive irreducible operation was modified to primitive irreducible trinomial $x^m+x+1$ that satisfies the range of 1$x^m,{\cdots},x^{2m-2}\;to\;x^{m-1},{\cdots},x^0$ is reduced. In this paper, the primitive irreducible polynomial was reduced to the primitive irreducible trinomial proposed. As a result of this reduction, the primitive irreducible trinomial reduced the size of circuit. In addition, the proposed design of multiplier was suitable for VLSI implementation because the circuit became regular and modular in structure, and required simple control signal.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.11
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• pp.2507-2513
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• 2010

In this paper, we show that the shrinking generator with two LFSR whose characteristic polynomials are primitive is an interleaving generator and analyze phase shifts in shrunken sequence. Also for a given intercepted sequence of shrunken sequence, we propose. the method of reconstructing some deterministic bits of the shrunken sequence using phase shifts.

• Proceedings of the Korea Information Processing Society Conference
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• 2003.11c
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• pp.1839-1842
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• 2003

핑거프린팅은 컨텐츠 유통 시, 구매자의 정보를 컨텐츠에 삽입함으로써 불법 유통 행위된 컨텐츠에 대하여 불법 배포자를 추적할 수 있는 기법이다. 이 방법에는 서로 다른 구매자에 의한 핑거프린팅코드를 제거하려는 공모 공격(collusion attacks)이 발생할 수 있다. 본 논문에서는 고차의 원시다항식을 이용하여 효율적이면서 공모 공격에 강인한 핑거프린팅 코드 구성 방법을 제안한다. 그리고, 제안된 방법을 오디오 데이터에 적용하여 공모 공격에 대하여 안전한 코드임을 보이고 있다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.3
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• pp.707-714
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• 2010

Since an LFSR(linear feedback shift register) as a pattern generator has solely linear dependency in itself, it generates sequences by moving the bit positions for pattern generation. So the correlation between the generated patterns is high and thus reduces the possibility of fault detection. To overcome these problems many researchers studied to have goodness of randomness between the output test patterns. In this paper, we propose the new and effective method to construct phase shifter as PRPG(pseudo random pattern generator).