• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.884-888
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• 1987

Error control performance of punctured convolutional codes is considered in digital mobile radio communication wherein GMSK and DQPSK are assumed to be employed as a modulation scheme. Bit error rates of the two modulation systems with the punctured convolutional code are computed, and compared each other, some good punctured convolutional codes are searched and listed fork practical application to the digital mobile radio communication.

• The KIPS Transactions:PartB
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• v.9B no.5
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• pp.571-578
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• 2002

In this paper, we propose a video sequence coding scheme called AMV (Auxiliary Motion Vector) to minimize error propagation caused by transmission errors over the Internet. Unlike the conventional coding schemes the AMY coder, for a macroblock in a frame, selects two best matching blocks among several preceding frames. The best matching block, called a primary block, is used for motion compensation of the destination macroblock. The other block, called an auxiliary block, replaces the primary block in case of its loss at the decoder. When a primary block is corrupted or lost during transmission, the decoder can efficiently and simply suppress error propagation to the subsequent frames by replacing the block with an auxiliary block. This scheme has an advantage of reducing both the number and the impact of error propagations. We implemented the proposed coder by modifying H.263 standard coding and evaluated the performance of our proposed scheme in the simulation. The simulation results show that AMV coder is more efficient than the H.263 baseline coder at the high packet loss rate.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.11
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• pp.87-92
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• 2005

This paper analyzes the performance for an improved multistage parallel interference cancellation (PIC) technique with a reverse-link synchronous transmission technique (RLSTT) for DS-CDMA system in a frequency-selective Rayleigh fading channel with an imperfect power control scheme. The performance degradation due to power control error (PCE), which is approximated by a log-normally distributed random variable, is estimated as a function of the standard deviation of the PCE. The uncoded bit error performance is evaluated in order to estimate the system capacity. Comparing with the conventional one-stage PIC system, we show achievable gain around $60\%$ by the RLSTT even in the presence of PCE. We conclude that the capacity can be further improved via RLSTT, which alleviates the detrimental effects of the PCE

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.7B
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• pp.1351-1360
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• 1999

In frequency selective channels, conventional PN code acquisition schemes are not ideal candidates. This is because they are primarily designed for the AWGN channel. In this paper, a direct-sequence spread-spectrum(DSSS) PN code acquisition system based on digital matched filtering (DMF) with automatic threshold control(ATC) algorithm is presented and analyzed with regards to probability of detection and probability of false alarm. These two important probabilities, the probability of detection ($P_D$) and the probability of false alarm ($P_{FA}$) are derived and analyzed in considering Doppler shift, sampling rate, mean acquisition time, and PN chip rate in frequency selective Rayleigh fading channel when using serial-search method as detection technique. From computer simulation results of a DMF acquisition system model, it is shown that the performance of the acquisition system using ATC algorithm is better than that of constant threshold system.

• The Journal of Information Technology
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• v.7 no.3
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• pp.37-45
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• 2004

The representative communication method which is applied in the low-speed power line communication modem with 60bps is single carrier method. It has been used mainly for the control. The single carrier method is very sensitive to a power line communication channel environment. Specially, the severe attenuation of the transmission signal according to the notch characteristics of channel becomes the main cause of communication error. Domestic power line channel environment has this notable feature. In this paper, we implemented the low-speed power line communication system which used the chirp signal method to be strong in notch and noise characteristics. In this research, we proposed the method which transmits 1- '1 Unit symbol Chirp signal' with a 100${\mu}s$ time within 1ms for 1 bit. Also it applied for the Convolution code for an error correction and the Manchester code for a collision perception and an error detection. It used the method which uses the bit correlator for signal detection in the receiver parts. We confirmed that the communication method of the chirp method has a excellent performance compared to single carrier methods with a result of experiment of the low-speed power line communication system with the 60bps.

• Journal of Advanced Navigation Technology
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• v.15 no.6
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• pp.1075-1081
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• 2011

In this paper, we proposed the DS-SS modem-based communication system for long distance wireless-transmission. The module we designed in this approach contained both convolution encoder and gold-code generator, which aimed at error correcting, T-DES encryption algorithm and spread-spectrum as well. It embodied PC-based GUI program in order to control the such command signal as data transceiver. This program also used to control the specific FPGA/MCU which is able to verify and interface to the modem. We demonstrated the communication system to verify its proper operation by using GUI program and designed hardware. A set of experiments are conducted and as a result, proposed communication system is well operated as the design specification.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.11
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• pp.51-62
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• 2003

This paper presents a novel survivor memeory management and decoding techniques with sequential backward state transition control in the trace back Viterbi decoder. The Viterbi algorithm is an maximum likelihood decoding scheme to estimate the likelihood of encoder state for channel error detection and correction. This scheme is applied to a broad range of digital communication such as intersymbol interference removing and channel equalization. In order to achieve the area-efficiency VLSI chip design with high throughput in the Viterbi decoder in which recursive operation is implied, more research is required to obtain a simple systematic parallel ACS architecture and surviver memory management. As a method of solution to the problem, this paper addresses a progressive decoding algorithm with sequential backward state transition control in the trace back Viterbi decoder. Compared to the conventional trace back decoding techniques, the required total memory can be greatly reduced in the proposed method. Furthermore, the proposed method can be implemented with a simple pipelined structure with systolic array type architecture. The implementation of the peripheral logic circuit for the control of memory access is not required, and memory access bandwidth can be reduced Therefore, the proposed method has characteristics of high area-efficiency and low power consumption with high throughput. Finally, the examples of decoding results for the received data with channel noise and application result are provided to evaluate the efficiency of the proposed method.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.17 no.1
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• pp.33-39
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• 2007

Finite field multipliers are the basic building blocks in many applications such as error-control coding, cryptography and digital signal processing. Hence, the design of efficient dedicated finite field multiplier architectures can lead to dramatic improvement on the overall system performance. In this paper, a new bit serial structure for a multiplier with low latency in Galois field is presented. To speed up multiplication processing, we divide the product polynomial into several parts and then process them in parallel. The proposed multiplier operates standard basis of $GF(2^m)$ and is faster than bit serial ones but with lower area complexity than bit parallel ones. The most significant feature of the proposed architecture is that a trade-off between hardware complexity and delay time can be achieved.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.7C
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• pp.726-732
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• 2003

The paper proposes a motion estimation (ME) technique to reduce computational complexity. It is achieved by skipping ME process for macro-blocks decided to be in no need of the operation. Thus, it is called ME skipping technique(MEST). In general, the ME is composed of integer pixel precision ME (IME) followed by half pixel precision ME (HME). The MEST is performed just before an IME process and makes a decision on skipping the IME process according to a criterion based on ME errors of adjacent macro-blocks (MBs) already encoded. When the IME process for a MB is decided to be skipped, which is called ME skip mode, the IME process is skipped and the integer pixel precision motion vector of the MB is just replaced by a predicted vector and used as the input of HME. On the other hands, the IME processes for MBs in ME non-skip mode are not skipped but normally performed. Accordingly, the MEST is very effective to reduce computational complexity when MBs in ME skip mode is abundant. In addition, when the MEST is applied to video encoder, it contributes to more accurate rate control and more robusaess for channel errors. It is experimentally shown that the MEST has the above advantages while maintaining good reconstructed image quality.