• Korean journal of food and cookery science
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• v.3 no.1
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• pp.37-46
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• 1987

SULNONGTANG is a kind of “goomkok”-korean typical soup made with beef, tone and organs, and is belived to be as a good source of portein and calcium, but there is no standard formulation for that. In order to set up the standard formulation of SULNONGTANG cooking method, I have performed a nutritional analysis of change in the components of SULNONGTANG, which contained the proximate composition, free amino acids, nucleotides, cholesterol, calium, phosphorus and iron. The conventional SULNONGTANG were cooked by conventional methods varing cooking time and ingredient. And also the current Market SULNONGTANG were cooked by the same methods for conventional SULNONGTANG and adding beef's head, hooves or knee tones. The result obtained in this study were as fallows: 1. In case of conventional SULNONGTANG, the most desirable cooking time was from 12 to 18 hours, the preparation method for group A was the best to maintain the optimal amount of nutrients and 5'-IMP. 2. In Market SULNONGTANG, nutritional contents were poorer than that of conventional SULNONGTANG. When the beef's head was added to the Market SULNONGTANG, nutritional status were more desirable than those added hooves or knee bones.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.16 no.6
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• pp.509-518
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• 2023

In this paper, we designed a 4Kb poly-fuse OTP IP (Intellectual Property) required for analog circuit trimming and calibration. In order to reduce the BL resistance of the poly-fuse OTP cell, which consists of an NMOS select transistor and a poly-fuse link, the BL stacked metal 2 and metal 3. In order to reduce BL routing resistance, the 4Kb cells are divided into two sub-block cell arrays of 64 rows × 32 rows, with the BL drive circuit located between the two 2Kb sub-block cell arrays, which are split into top and bottom. On the other hand, in this paper, we propose a core circuit for an OTP cell that uses one poly-fuse link to one select transistor. In addition, in the early stages of OTP IP development, we proposed a data sensing circuit that considers the case where the resistance of the unprogrammed poly-fuse can be up to 5kΩ. It also reduces the current flowing through an unprogrammed poly-fuse link in read mode to 138㎂ or less. The poly-fuse OTP cell size designed with DB HiTek 90nm CMOS process is 11.43㎛ × 2.88㎛ (=32.9184㎛2), and the 4Kb poly-fuse OTP IP size is 432.442㎛ × 524.6㎛ (=0.227mm²).

• Journal of Animal Environmental Science
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• v.10 no.3
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• pp.141-154
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• 2004

The solar powered water pump is very ideal equipment because solar power is more intensive when the water is more needed in summer and it is very helpful in the rural area, in which the electrical power is not available. The average so]ar radiation energy is 3.488 kWh/($m^2{\cdot}day$) in Korea. In this study, the automatic control logic and system of the water pump driven by the radiation energy were studied, designed, assembled, tested and analyzed for realizing the solar powered water pump. The experimental system was operated automatically and the cycle was continued. The average quantity of the water pumped per cycle was about 5,320 cc. The cycle time was about 4.9 minutes. The thermal efficiency of the system was about $0.030\%$. The pressure level of the n-pentane vapour in flash tank was 150$\%$450 hPa(gauge) which was set by the computer program for the control of the vapour supply. The pressure in the condenser and air tank during cycles was maintained as about 600 hPa and 1,200 hPa respectively. The water could be pumped by the amount of 128kg/($m^2{\cdot}day$) with the efficiency of $0.1\%$ and the pumping head of 10 m for the average solar energy in Korea.

• Polymer(Korea)
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• v.36 no.3
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• pp.275-280
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• 2012

Poly(amic acid)s were successfully synthesized from 1,4-bis(4-aminophenoxy)benzene (1,4-APB) or 2,2-bis[4-(4-aminophenoxy)phenyl]hexafluoropropane (HFBAPP) with pyromellitic dianhydride (PMDA), 3,3'-4,4'-benzopenonetetracarboxylic dianhydride (BPDA) and $p$-phenylenediamine ($p$-PDA) and then they were effectively converted into polyimide films by thermal imidization. The chemical structure and thermo-mechanical properties of polyimide films were examined using Fourier transform infrared spectroscopy (FTIR), thermo-gravimetric analyzer (TGA), thermo-mechanical analyzer, dynamic mechanical analyzer (DMA) and universal tensile machine (UTM). The moisture absorption, thermal and mechanical properties of polyimide films decreased with increasing the amount of 1,4-APB and HFBAPP. The polyimide films using HFBAPP showed lower properties than that of 1,4-APB at the same ratio, but it displayed better thermal properties and lower moisture absorption at the similar coefficient of thermal expansion (CTE) with a copper. On the basis of our finding, it is concluded that 4-component polyimide films could be utilized for base films for flexible copper clad laminates (FCCL) of flexible printed circuit boards.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.53-63
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• 2009

This work proposes a 10b 100MS/s 27.2mW $0.8mm^2$ 0.18um CMOS ADC for WLAN such as an IEEE 802.11n standard. The proposed ADC employs a three-stage pipeline architecture and minimizes power consumption and chip area by sharing as many circuits as possible. Two multiplying DACs share a single amplifier without MOS switches connected in series while the shared amplifier does not show a conventional memory effect. All three flash ADCs use only one resistor ladder while the second and third flash ADCs share all pre-amps to further reduce power consumption and chip area. The interpolation circuit employed in the flash ADCs halves the required number of pre-amps and an input-output isolated dynamic latch reduces the increased kickback noise caused by the pre-amp sharing. The prototype ADC implemented in a 0.18um n-well 1P6M CMOS process shows the DNL and INL within 0.83LSB and 1.52LSB at 10b, respectively. The ADC measures an SNDR of 52.1dB and an SFDR of 67.6dB at a sampling rate of 100MS/s. The ADC with an active die area of $0.8mm^2$ consumes 27.2mW at 1.8V and 100MS/s.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.39 no.6
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• pp.526-534
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• 2011

The MFS (Mlti-Functional Structure) concept, which integrates the electronics, thermal control and structure into a single packaging system, has been developed and applied to reduce the volume and weight of the satellite. Therefore, this MFS can eliminate the bulky chassis/frames, cables and connectors of the electronic equipment. The main point of this traditional MFS is the replacement of the electrical chassis/frames with MCMs (Multi-Chip Modules) that require much costs and efforts for developing. This paper shows the new MFS concept that effectively saves the volume and weight. The structure including the thermal control and radiation shielding elements will be designed and manufactured as the rectangular grid-stiffened structure. The rectangular grid-stiffened structure is the modification of the iso-grid structure, and provides the enough spaces for putting the general PCBs without the chassis/frames.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.7A
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• pp.683-694
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• 2002

In this paper, a digital image compression codec using 2D DWT(Discrete Wavelet Transform) is designed using the FPGA technology for real time operation The implemented image compression codec using wavelet decomposition consists of a wavelet kernel part for wavelet filtering process, a quantizer/huffman coder for quantization and huffman encoding of wavelet coefficients, a memory controller for interface with external memories, a input interface to process image pixels from A/D converter, a output interface for reconstructing huffman codes, which has irregular bit size, into 32-bit data having regular size data, a memory-kernel buffer to arrage data for real time process, a PCI interface part, and some modules for setting timing between each modules. Since the memory mapping method which converts read process of column-direction into read process of the row-direction is used, the read process in the vertical-direction wavelet decomposition is very efficiently processed. Global operation of wavelet codec is synchronized with the field signal of A/D converter. The global hardware process pipeline operation as the unit of field and each field and each field operation is classified as decomposition levels of wavelet transform. The implemented hardware used FPGA hardware resource of 11119(45%) LAB and 28352(9％) ESB in FPGA device of APEX20KC EP20k600CB652-7 and mapped into one FPGA without additional external logic. Also it can process 33 frames(66 fields) per second, so real-time image compression is possible.

• Journal of the Microelectronics and Packaging Society
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• v.6 no.2
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• pp.37-43
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• 1999

Modules of the system that requires large capacity and high-speed information processing are implemented in the form of MCM that allows high-speed data processing, high density circuit integration and widely applied to such fields as ATM, GPS and PCS. Hence we developed the ATM switching module that is consisted of three chips and 2.48 Gbps data throughput, in the form of 10 multi-layer by Cu/Photo-BCB and 491pin PBGA which size is $48 \times 48 \textrm {mm}^2$. hnologies required for the development of the MCM includes extracting parameters for designing the substrate/package through the interconnect characterization to implement the high-speed characteristics, thermal management at the high-density MCM, and the generation of the testability that is one of the most difficult issues for developing the MCM. For the development of the ATM Switching MCM, we extracted signaling delay, via characteristics and crosstalk parameters through the interconnect characterization on the MCM-D. For the thermal management of 15.6 Watt under the high-density structure, we carried out the thermal analysis. formed 1.108 thermal vias through the substrate, and performed heat-proofing processing for the entire package so that it can keep the temperature less than $85^{\circ}C$. Lastly, in order to ensure the testability, we verified the substrate through fine pitch probing and applied the Boundary Scan Test (BST) for verifying the complex packaging/assembling processes, through which we developed an efficient and cost-effective product.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.20 no.6
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• pp.598-603
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• 2019

Three-dimensional shape measurement technology is used in various industries. Among them, optical three-dimensional shape measurement techniques based on the optical trigonometry are mainly used in the field of semiconductor product inspection, where large quantities of three-dimensional shape measurements are made daily in factories and fine measurements are also required. The light source and the drive circuit, which are components of three-dimensional measurement equipment based on this optical trigonometry, produce heat generated by prolonged operation, and may be exposed to conditions where the ambient temperature is not constant, resulting in temperature-induced measurement errors. In this study, the compensation method of the Thermal Errors for Phase Measuring Profilometry is proposed. Three-Dimensional Shape Measurement Equipment based on Phase Measuring Profilometry is implemented to measure the height of an object and ambient temperature for 10 Hours, and a regression line was obtained line by making simple linear regression using measured temperature and height values. This regression line was used to correct the error of the height measurement according to the temperature, and thermal error was from 139.88 um(Micrometer) to 13.12 um.

• Journal of the Microelectronics and Packaging Society
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• v.29 no.3
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• pp.55-61
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• 2022

In this study, properties of Pb-free solder joints which were combined using Sn-3.0Ag-0.5Cu (SAC305) Pb-free solder with a mid-temperature type of melting temperature and Sn-57Bi-1Ag Pb-free solder with a low-temperature type of melting temperature were reported. Combined Pb-free solder joints were formed by reflow soldering processes with ball grid array (BGA) packages which have SAC305 solder balls and flame retardant-4 (FR-4) printed circuit boards (PCBs) which printed Sn-57Bi-1Ag solder paste. The reflow soldering processes were performed with two types of temperature profiles and interfacial properties of combined Pb-free solder joints such as interfacial reactions, formations of intermetallic compounds (IMCs), diffusion mechanisms of Bi, and so on were analyzed with the reflow process conditions. In order to compare reliability characteristics of combined Pb-free solder joints, we also conducted thermal shock test and analyzed changes of mechanical properties for joints from a shear test during the thermal shock test.