• Journal of KIISE:Computer Systems and Theory
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• v.30 no.1
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• pp.50-58
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• 2003

Among finite field arithmetic operations, the $AB^2$ operation is known as an efficient basic operation for public key cryptosystems over $GF(2^m)$,Division/Inversion is computed by performing the repetitive AB$^2$ multiplication. This paper presents two new $AB^2$algorithms and their systolic realizations in finite fields $GF(2^m)$.The proposed algorithms are based on the MSB-first scheme using standard basis representation and the proposed systolic architectures for $AB^2$ multiplication have a low hardware complexity and small latency compared to the conventional approaches. Additionally, since the proposed architectures incorporate simplicity, regularity, modularity, and pipelinability, they are well suited to VLSI implementation and can be easily applied to inversion architecture. Furthermore, these architectures will be utilized for the basic architecture of crypto-processor.

• The Journal of the Korea Contents Association
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• v.7 no.1
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• pp.147-154
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• 2007

In this paper, we propose a new parallel search algorithm to acquire synchronization for UWB(Ultra Wideband) systems that reduces computation of the correlation. The conventional synchronization acquisition algorithms check all the possible signal phases simultaneously using multiple correlators. However it reduces the acquisition time, it makes high power consumption owing to increasing of correlation. The proposed algorithm divides the preamble signal to input the correlator into an m-bit bunch. We check the result of the correlation at first stage of an m-bit bunch data and predict whether it has some synchronization acquisition information or not. Thus, it eliminates the unnecessary operation and save the number of correlation. We evaluate the proposed algorithm under the AWGN and the multi-Path channel model with MATLAB. The proposed parallel search scheme reduces number of the correlation 65% on the AWGN and 20% on the multi-path fading channel.

• Journal of the Korean Institute of Intelligent Systems
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• v.14 no.4
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• pp.418-423
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• 2004

The motion estimation algorithm based block matching is a widely used in the international standards related to video compression, such as the MPEG series and H.26x series. Full search algorithm(FA) ones of this block matching algorithms is usually impractical because of the large number of computations required for large search region. Fast search algorithms and conventional binary block matching algorithms reduce computational complexity and data processing time but this algorithms have disadvantages that is less performance than full search algorithm. This paper presents new Boolean matching algorithm, called BCBM(Bit Converted Boolean Matching). Proposed algorithm has performance closed to the FA by Boolean only block matching that may be very efficiently implemented in hardware for real time video communication. Simulation results show that the PSNR of the proposed algorithm is about 0.08㏈ loss than FA but is about 0.96∼2.02㏈ gain than fast search algorithm and conventional Boolean matching algorithm.

• Journal of IKEEE
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• v.17 no.4
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• pp.418-427
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• 2013

In this paper, we propose a parallel deblocking filter algorithm for H.264/AVC video standard. The deblocking filter has different filter processes according to boundary strength (BS) and each filter process requires various conditional calculations. The order of filtering makes it difficult to parallelize deblocking filter calculations. The proposed deblocking filter algorithm is performed on PRAGRAM which is a 1-D coarse grained reconfigurable architecture (CGRA). Each filter calculation is accelerated using uni-directional pipelined architecture of PRAGRAM. The filter selection and the conditional calculations are efficiently performed using dynamic reconfiguration and conditional reconfiguration. The parallel deblocking filter algorithm uses 225 cycles to process a macroblock and it can process a full HD image at 150 MHz.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.12
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• pp.41-50
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• 1999

In this paper, the new VLSI architecture of a reconstruction filter for morphological image segmentation is proposed. The filter, based on the $h_{max}$ operation, simplifies the interior of each region while preserving the boundary information. The proposed architecture adopts a partitioned memory structure and an efficient image scanning strategy to reduce the operations. The proposed memory partitioning scheme makes it possible that every data required for processing can be read from each memory at a time, resulting in parallel data processing. By the extended connectivity consideration, the operation is much decreased because more simplification is achieved in scanning stage. The selective raster scan strategy endows the satisfactory noise removal capability with negligible hardware complexity increase. The proposed architecture is designed using VHDL, and functional evaluation is performed by the CAD tool, Mentor. The experiment results show that the proposed architecture can simplify image profile with less than 18% operations of the conventional method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.10
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• pp.85-94
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• 2004

In this paper, a register allocation techlique that translates memory accesses to register accesses Is presented to enhance embedded software performance. In the proposed method, a source code is profiled to generate a memory trace. From the profiling results, target functions with high dynamic call counts are selected, and the proposed register allocation technique is applied only to the target functions to save the compilation time. The memory trace of the target functions is searched for the memory accesses that result in cycle count reduction when replaced by register accesses, and they are translated to register accesses by modifying the intermediate code and allocating Promotion registers. The experiments where the performance is measured in terms of the cycle count on MediaBench and DSPstone benchmark programs show that the proposed method increases the performance by 14% and 18% on the average for ARM and MCORE, respectively.

• The KIPS Transactions:PartC
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• v.19C no.1
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• pp.9-18
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• 2012

In 2010, Pedro et al. proposed RFID distance bounding protocol based on WSBC cryptographic puzzle. This paper points out that Pedro et al.'s protocol not only is vulnerable to tag privacy invasion attack and location tracking attack because an attacker can easily obtain the secret key(ID) of a legal tag from the intercepted messages between the reader and the tag, but also requires heavy computation by performing symmetric key operations of the resource limited passive tag and many communication rounds between the reader and the tag. Moreover, to resolve the security weakness and the computation/communication efficiency problems, this paper also present a new RFID distance bounding protocol based on WSBC cryptographic puzzle that can provide strong security and high efficiency. As a result, the proposed protocol not only provides computational and communicational efficiency because it requires secure one-way hash function for the passive tag and it reduces communication rounds, but also provides strong security because both tag and reader use secure one-way hash function to protect their exchanging messages.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.13 no.5
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• pp.3-15
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• 2003

The secure group communication enables the members, which belong to the same group, to communicate each other in a secure and secret manner. To do so, it is the most important that a group key is securely distributed among them and also group membership is efficiently managed. In detail, the generation, the distribution and the refreshment of a group key would be highly regarded in terms of low communication and computation complexity. In this paper, we show you a new protocol to generate a group key which will be safely shared within a group, utilizing the 2-party Diffie-Hellman key exchange protocol and the complete binary tree. Our protocol has less complexity of computation per group member by substituting many parts of exponentiation computations for multiplications. Consequently, each group member needs constant computations of exponentiation and multiplication regardless of the group size in the protocol and then it has less complexity of the computation than that of any other protocols.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.11
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• pp.2503-2510
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• 2012

This paper proposes a parallel operation intra predictor for H.264/AVC decoder. In previous intra predictor design, common operation units were designed for 17 prediction modes in order to compute more effectively. However, it was designed by analyzing the equation applied to one pixel. So, there are four operation units for computing 16 pixels in a $4{\times}4$ block and they need four cycles. In this paper, the proposed intra predictor contains T3(Three Type Transform) operation unit for parallel operation. It divides 17 modes into 3 types to calculate 16 pixels of a $4{\times}4$ block in only one cycle and needs 16 cycles minimum in 16x16 block. As the result of the experiment, in terms of processing cycle, the performance of proposed intra predictor is 58.95% higher than the previous one.

• Journal of Digital Contents Society
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• v.2 no.2
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• pp.103-115
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• 2001

This paper proposes the two algorithms which generate a minimal decision rule and approximate inference operation, adapted the rough set and the factor space theory in fuzzy knowledge base. The generation of the minimal decision rule is executed by the data classification technique and reduct applying the correlation analysis and the Bayesian theorem related attribute factors. To retrieve the specific object, this paper proposes the approximate inference method defining the membership function and the combination operation of t-norm in the minimal knowledge base composed of decision rule. We compare the suggested algorithms with the other retrieval theories such as possibility theory, factor space theory, Max-Min, Max-product and Max-average composition operations through the simulation generating the object numbers and the attribute values randomly as the memory size grows. With the result of the comparison, we prove that the suggested algorithm technique is faster than the previous ones to retrieve the object in access time.