• Title/Summary/Keyword: 에지검출

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Reduction of Radiographic Quantum Noise Using Adaptive Weighted Median Filter (적응성 가중메디안 필터를 이용한 방사선 투과영상의 양자 잡음 제거)

  • Lee, Hoo-Min;Nam, Moon-Hyon
    • Journal of the Korean Society for Nondestructive Testing
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    • v.22 no.5
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    • pp.465-473
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    • 2002
  • Images are easily corrupted by noise during the data transmission, data capture and data processing. A technical method of noise analyzing and adaptive filtering for reducing of quantum noise in radiography is presented. By adjusting the characteristics of the filter according to local statistics around each pixel of the image as moving windowing, it is possible to suppress noise sufficiently while preserve edge and other significant information required in reading. We have proposed adaptive weighted median(AWM) filters based on local statistics. We show two ways of realizing the AWM filters. One is a simple type of AWM filter, whose weights are given by a simple non-linear function of three local characteristics. The other is the AWM filter which is constructed by homogeneous factor(HF). Homogeneous factor(HF) from the quantum noise models that enables the filter to recognize the local structures of the image is introduced, and an algorithm for determining the HF fitted to the detection systems with various inner statistical properties is proposed. We show by the experimented that the performances of proposed method is superior to these of other filters and models in preserving small details and suppressing the noise at homogeneous region. The proposed algorithms were implemented by visual C++ language on a IBM-PC Pentium 550 for testing purposes, the effects and results of the noise filtering were proposed by comparing with images of the other existing filtering methods.

Development of CPLD Technology Mapping Algorithm for Sequential Circuit Improved Run-Time Under Time Constraint (시간제약 조건하에서 순차 회로를 위한 수행시간을 개선한 CPLD 기술 매핑 알고리즘 개발)

  • Yun, Chung-Mo;Kim, Hui-Seok
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.37 no.4
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    • pp.80-89
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    • 2000
  • In this paper, we propose a new CPLD technology mapping algorithm for sequential circuit under time constraints. The algorithm detects feedbacks of sequential circuit, separate each feedback variables into immediate input variable, and represent combinational part into DAG. Also, among the nodes of the DAG, the nodes that the number of outdegree is more than or equal to 2 is not separated, but replicated from the DAG, and reconstructed to fanout-free-tree. To use this construction method is for reason that area is less consumed than the TEMPLA algorithm to implement circuits, and process time is improved rather than TMCPLD within given time constraint. Using time constraint and delay of device the number of partitionable multi-level is defined, the number of OR terms that the initial costs of each nodes is set to and total costs that the$^1$costs is set to after merging nodes is calculated, and the nodes that the number of OR terms of CLBs that construct CPLD is excessed is partitioned and is reconstructed as subgraphs. The nodes in the partitioned subgraphs is merged through collapsing, and the collapsed equations is performed by bin packing so that it fit to the number of OR terms in the CLBs of a given device. In the results of experiments to MCNC circuits for logic synthesis benchmark, we can shows that proposed technology mapping algorithm reduces the number of CLBs by 15.58% rather than the TEMPLA, and reduces process time rather than the TMCPLD.

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A Study On Low-cost LPR(License Plate Recognition) System Based On Smart Cam System using Android (안드로이드 기반 스마트 캠 방식의 저가형 자동차 번호판 인식 시스템 구현에 관한 연구)

  • Lee, Hee-Yeol;Lee, Seung-Ho
    • Journal of IKEEE
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    • v.18 no.4
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    • pp.471-477
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    • 2014
  • In this paper, we propose a low-cost license plate recognition system based on smart cam system using Android. The proposed system consists of a portable device and server. Potable device Hardware consists of ARM Cortex-A9 (S5PV210) processor control unit, a power supply device, wired and wireless communication, input/output unit. We develope Linux kernel and dedicated device driver for WiFi module and camera. The license plate recognition algorithm is consisted of setting candidate plates areas with canny edge detector, extracting license plate number with Labeling, recognizing with template matching, etc. The number that is recognized by the device is transmitted to the remote server via the user mobile phone, and the server re-transfer the vehicle information in the database to the portable device. To verify the utility of the proposed system, user photographs the license plate of any vehicle in the natural environment. Confirming the recognition result, the recognition rate was 95%. The proposed system was suitable for low cost portable license plate recognition device, it enabled the stability of the system when used long time by using the Android operating system.

Development of CPLD technology mapping algorithm for Sequential Circuit under Time Constraint (시간제약 조건하에서 순차 회로를 위한 CPLD 기술 매핑 알고리즘 개발)

  • Youn, Chung-Mo;Kim, Hi-Seok
    • The Transactions of the Korea Information Processing Society
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    • v.7 no.1
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    • pp.224-234
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    • 2000
  • In this paper, we propose a new CPLD technology mapping algorithm for sequential circuit under time constraints. The algorithm detects feedbacks of sequential circuit, separate each feedback variables into immediate input variable, and represent combinational part into DAG. Also, among the nodes of the DAG, the nodes that the number of outdegree is more than or equal to 2 is not separated, but replicated from the DAG, and reconstructed to fanout-free-tree. To use this construction method is for reason that area is less consumed than the TEMPLA algorithm to implement circuits, and process time is improved rather than TMCPLD within given time constraint. Using time constraint and delay of device the number of partitionable multi-level is defined, the number of OR terms that the initial costs of each nodes is set to and total costs that the costs is set to after merging nodes is calculated, and the nodes that the number of OR terms of CLBs that construct CPLD is excessed is partitioned and is reconstructed as subgraphs. The nodes in the partitioned subgraphs is merged through collapsing, and the collapsed equations is performed by bin packing so that if fit to the number of OR terms in the CLBs of a given device. In the results of experiments to MCNC circuits for logic synthesis benchmark, we can shows that proposed technology mapping algorithm reduces the number of CLBs bu 15.58% rather than the TEMPLA, and reduces process time rather than the TMCPLD.

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An Efficient CPLD Technology Mapping considering Area under Time Constraint (시간 제약 조건하에서 면적을 고려한 효율적인 CPLD 기술 매핑)

  • Kim, Jae-Jin;Kim, Hui-Seok
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.38 no.1
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    • pp.79-85
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    • 2001
  • In this paper, we propose a new technology mapping algorithm for CPLD consider area under time constraint(TMFCPLD). This technology mapping algorithm detect feedbacks from boolean networks, then variables that have feedback are replaced to temporary variables. Creating the temporary variables transform sequential circuit to combinational circuit. The transformed circuits are represented to DAG. After traversing all nodes in DAG, the nodes that have output edges more than two are replicated and reconstructed to fanout free tree. This method is for reason to reduce area and improve total run time of circuits by TEMPLA proposed previously. Using time constraints and delay time of device, the number of graph partitionable multi-level is decided. Initial cost of each node are the number of OR-terms that it have. Among mappable clusters, clusters of which the number of multi-level is least is selected, and the graph is partitioned. Several nodes in partitioned clusters are merged by collapsing, and are fitted to the number of OR-terms in a given CLB by bin packing. Proposed algorithm have been applied to MCNC logic synthesis benchmark circuits, and have reduced the number of CLBs by 62.2% than those of DDMAP. And reduced the number of CLBs by 17.6% than those of TEMPLA, and reduced the number of CLBs by 4.7% than those of TMCPLD. This results will give much efficiency to technology mapping for CPLDs.

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Accelerated Convolution Image Processing by Using Look-Up Table and Overlap Region Buffering Method (Loop-Up Table과 필터 중첩영역 버퍼링 기법을 이용한 컨벌루션 영상처리 고속화)

  • Kim, Hyun-Woo;Kim, Min-Young
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.49 no.4
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    • pp.17-22
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    • 2012
  • Convolution filtering methods have been widely applied to various digital signal processing fields for image blurring, sharpening, edge detection, and noise reduction, etc. According to their application purpose, the filter mask size or shape and the mask value are selected in advance, and the designed filter is applied to input image for the convolution processing. In this paper, we proposed an image processing acceleration method for the convolution processing by using two-dimensional Look-up table (LUT) and overlap-region buffering technique. First, based on the fixed convolution mask value, the multiplication operation between 8 or 10 bit pixel values of the input image and the filter mask values is performed a priori, and the results memorized in LUT are referred during the convolution process. Second, based on symmetric structural characteristics of the convolution filters, inherent duplicated operation region is analysed, and the saved operation results in one step before in the predefined memory buffer is recalled and reused in current operation step. Through this buffering, unnecessary repeated filter operation on the same regions is minimized in sequential manner. As the proposed algorithms minimize the computational amount needed for the convolution operation, they work well under the operation environments utilizing embedded systems with limited computational resources or the environments of utilizing general personnel computers. A series of experiments under various situations verifies the effectiveness and usefulness of the proposed methods.

Emotion-based Video Scene Retrieval using Interactive Genetic Algorithm (대화형 유전자 알고리즘을 이용한 감성기반 비디오 장면 검색)

  • Yoo Hun-Woo;Cho Sung-Bae
    • Journal of KIISE:Computing Practices and Letters
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    • v.10 no.6
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    • pp.514-528
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    • 2004
  • An emotion-based video scene retrieval algorithm is proposed in this paper. First, abrupt/gradual shot boundaries are detected in the video clip representing a specific story Then, five video features such as 'average color histogram' 'average brightness', 'average edge histogram', 'average shot duration', and 'gradual change rate' are extracted from each of the videos and mapping between these features and the emotional space that user has in mind is achieved by an interactive genetic algorithm. Once the proposed algorithm has selected videos that contain the corresponding emotion from initial population of videos, feature vectors from the selected videos are regarded as chromosomes and a genetic crossover is applied over them. Next, new chromosomes after crossover and feature vectors in the database videos are compared based on the similarity function to obtain the most similar videos as solutions of the next generation. By iterating above procedures, new population of videos that user has in mind are retrieved. In order to show the validity of the proposed method, six example categories such as 'action', 'excitement', 'suspense', 'quietness', 'relaxation', 'happiness' are used as emotions for experiments. Over 300 commercial videos, retrieval results show 70% effectiveness in average.

Development of Video Image-Guided Setup (VIGS) System for Tomotherapy: Preliminary Study (단층치료용 비디오 영상기반 셋업 장치의 개발: 예비연구)

  • Kim, Jin Sung;Ju, Sang Gyu;Hong, Chae Seon;Jeong, Jaewon;Son, Kihong;Shin, Jung Suk;Shin, Eunheak;Ahn, Sung Hwan;Han, Youngyih;Choi, Doo Ho
    • Progress in Medical Physics
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    • v.24 no.2
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    • pp.85-91
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    • 2013
  • At present, megavoltage computed tomography (MVCT) is the only method used to correct the position of tomotherapy patients. MVCT produces extra radiation, in addition to the radiation used for treatment, and repositioning also takes up much of the total treatment time. To address these issues, we suggest the use of a video image-guided setup (VIGS) system for correcting the position of tomotherapy patients. We developed an in-house program to correct the exact position of patients using two orthogonal images obtained from two video cameras installed at $90^{\circ}$ and fastened inside the tomotherapy gantry. The system is programmed to make automatic registration possible with the use of edge detection of the user-defined region of interest (ROI). A head-and-neck patient is then simulated using a humanoid phantom. After taking the computed tomography (CT) image, tomotherapy planning is performed. To mimic a clinical treatment course, we used an immobilization device to position the phantom on the tomotherapy couch and, using MVCT, corrected its position to match the one captured when the treatment was planned. Video images of the corrected position were used as reference images for the VIGS system. First, the position was repeatedly corrected 10 times using MVCT, and based on the saved reference video image, the patient position was then corrected 10 times using the VIGS method. Thereafter, the results of the two correction methods were compared. The results demonstrated that patient positioning using a video-imaging method ($41.7{\pm}11.2$ seconds) significantly reduces the overall time of the MVCT method ($420{\pm}6$ seconds) (p<0.05). However, there was no meaningful difference in accuracy between the two methods (x=0.11 mm, y=0.27 mm, z=0.58 mm, p>0.05). Because VIGS provides a more accurate result and reduces the required time, compared with the MVCT method, it is expected to manage the overall tomotherapy treatment process more efficiently.