• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12A
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• pp.2059-2066
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• 2001

In this paper, we proposed a method to reduce the number of input pins in one-dimensional VLSI array for fractal image compression. We use quad-tree partition scheme and can reduce the number of the input pins up to 50% by sharing the domain\`s and the range\`s data input pins in the proposed VLSI array architecture. Also, we can reduce the input pins and simplify the internal operation circuit of the processing elements by eliminating a few number of bits of the least significant bits of the input data. We simulated using the 256$\times$256 and 512$\times$512 Lena images to verify performance of the proposed method. As the result of simulation, we can decompress the original image with about 32dB(PSNR) in spite of elimination of the least significant 2-bit in the original input data, and additionally reduce the number of input pins up to 25% compared to VLSI array sharing input pins of range and domain.

• Journal of Sensor Science and Technology
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• v.5 no.3
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• pp.65-73
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• 1996

One of the important factor in drug stuffs to a patient is to inject exact amount with stable flow rates. Since improper injection amount and flow rates would cause bad effect to recovery of a patient, the detecting sensors with high sensitivity is required for an injection pump systems' performance improvement. In this study, the three sensors, piezo film sensor, photo transistor and photo array, were compared to find best one for an injection pump monitoring system. Using suggested data processing technique and photo array sensors, we could minimize the effect of interference, disturbance, illumination, and sensitivity change caused by sensor's position. According to the experiments, the photo array showed the higher reliance than any other the three types of sensors.

• Journal of Sensor Science and Technology
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• v.8 no.4
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• pp.341-346
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• 1999

In general cases, compared with glass electrode, FET type electrolyte sensors have many advantages. But the drift, memory effect and the poor reproducibility of the FET type electrolyte sensor cause the decrease of the reliability in the measurement system. To improve the reliability, an ion-measuring system using FET type electrolyte sensor array with 8 sensors has been developed. Developed system employed the electronic switchs to connect a signal detecting circuit with 8 sensor array and the system can measure ion concentration of 4 different type electrolyte($H^+$, $Na^+$, $K^+$, $Ca^{2+}$). The signal processing algorithm with insertion sorting method was adopted to enhance the reliability. We measured 3 different ion($H^+$, $Na^+$, $K^+$) to evaluate the performance of developed system. The results show that the designed signal processing algorithm can reduce the error range in comparison with a simple arithmetic mean and the developed system has a good reliability over the previous single channel sensor system.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.4
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• pp.68-74
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• 2017

This paper presents a joint demosaicking and arbitrary-ratio down sampling algorithm for color filter array (CFA) images. Color demosaiking is a necessary part of image signal processing pipeline for many types of digital image recording system using single sensor. Also, such as smart phone, obtained high resolution image from image sensor has to be down-sampled to be displayed on the screen. The conventional solution is "Demosaicking first and down sampling later". However, this scheme requires a significant amount of memory and computational cost. Also, artifacts can be introduced or details get damaged during demosaicking and down sampling process. In this paper, we propose a method in which demosaicking and down sampling are working simultaneously. We use inverse mapping of Bayer CFA and then joint demosaicking and down sampling with arbitrary-ratio scheme based on signal decomposition of high and low frequency component in input data. Experimental results show that our proposed algorithm has better image quality performance and much less computational cost than those of conventional solution.

• Journal of IKEEE
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• v.9 no.1 s.16
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• pp.65-71
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• 2005

Physical signals generated in the real world are transformed into electrical signals through sensors and fed into electronic circuits. The electrical signals input to electronic circuits are in analog form, thus they must be converted to digital signals using an ADC(Analog-Digital Converter) for digital processing. Signal processing circuits and ADCs that are to be integrated on a single chip together with silicon micro sensors should be designed to have less silicon area and less power consumption. This paper proposed a charge redistribution ADC which reduces silicon area considerably. The proposed method achieves 8 bit conversion by performing 4-bit conversion twice. It reduced the area of capacitor array, which takes most of the ADC area, by 1/16 when compared to a conventional method. Though it uses twice the number of clocks as a conventional method, it would be appropriate to be integrated with a silicon pressure sensor on a single chip since it does not demand high conversion rate.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.1
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• pp.15-23
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• 2003

This paper proposes a fast direction of arrival (DOA) estimation algorithm that can rapidly estimate incidence angles of incoming signals using a pseudo covariance matrix. The conventional subspace DOA estimation methods such as MUSIC (multiple signal classification) algorithms need many sample signals to acquire covariance matrix of input signals. Thus, it is difficult to estimate the DOAs of signals because they cannot perform DOA estimation during receiving sample signals. Also if the D0As of signals are changing rapidly, conventional algorithms cannot estimate incidence angles of signals exactly. The proposed algorithm obtains bearing response and directional spectrum after acquiring pseudo covariance matrix of each snapshot. The incidence angles can be exactly estimated by using the bearing response and directional spectrum. The proposed DOA estimation algorithm uses only concurrent snapshot so as to obtain covariance matrix. Compared to conventional DOA estimation methods. The proposed algorithm has an advantage that can estimate DOA of signal rapidly.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.6
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• pp.1046-1055
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• 1994

In this paper, to design high speed 1 line VRAM(Video RAM) suitable for image signal processing with ASIC(Application Specific IC) method, the VRAM memory core has been designed using 3-TR dual-port dynamic cell which has excellent access time and integration characteristics. High speed pipeline operation was attained by separating the first row from the subarray 1 memory core and the simultaneous I/Q operation for a selected single address was made possible by adopting data-latch scheme. Peripheral circuits were designed implementing address selector and 1/2V voltage generator. Integrated ASIC has been optimized using 1.5[ m] CMOS design rule.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.8A
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• pp.1245-1251
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• 1999

A 1.25Gb/s path control switch chip has been designed and implemented with COMPASS tool and 0.8${\mu}{\textrm}{m}$ CMOS gate-array of LG semiconductor. This device controls the path of digital singnals in SDH-based transmission system. The proposed switch chip is suitable for self-healing operations both in a linear network and an unidirectonal ring, The self-healing operation of the switch is effectively done by the configuration information stored in the resisters of the switch. The test device adapted to SDH-based transmission system, show immediate restoration and a 10-11~10-12 bit error raito. And 2.5Gb/s or more high throughput can be realized by combining rwo identical or more switches with the parallel architecture.

• Journal of the Institute of Convergence Signal Processing
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• v.5 no.4
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• pp.317-324
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• 2004

Electromagnetically coupled coaxial dipole (ECCD) array antenna with and without short-ended termination is investigated theoretically. The integral equations are derived for the structure by use of the Fourier transform and mode expansion of radial waveguide. The integrals appearing in the integral equations are evaluated along the branch cut instead of real axis for a faster convergent integral. The effects of slots and dipoles, short-ended termination length, and dielectric coating on the radiation characteristics are presented. Radiation pattern of the structure is also investigated. The results of the present method are compared with those of the commercial EM simulator and good agreement is found.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.2
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• pp.451-456
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• 2016

Because GPS signals are weak, system jamming is a real and present danger. This can happen when the receiver is subjected to intentional or unintentional interference by a transmitter. If the jamming signal is strong enough, the receiver can be operated to take corrective action automatically. Current methods to protect GPS receiver from jamming condition are based on spatial filtering. In this paper, the beamforming as referred to in signal processing technique used in arrays for directional signal reception was suggested and analyzed for anti-jamming. In order to change the directionality of the array when receiving a jamming signal, a beamformer can control the signal at each sensor. Therefore, cutoff angle ${\theta}$ was measured in the opposite direction of the jammer. GPS signals are only processed when the antenna element is within inside the cutoff angle. As a result, GPS positioning can be used in condition under cutoff angle $30^{\circ}$.