• Title/Summary/Keyword: 심볼릭 모델 체킹

Search Result 2, Processing Time 0.016 seconds

Extending Model Checker for Real-time Verification of Statecharts (스테이트차트의 실시간 검증을 위한 모델체커의 확장)

  • 방호정;홍형석;김태효;차성덕
    • Journal of KIISE:Software and Applications
    • /
    • v.31 no.6
    • /
    • pp.773-783
    • /
    • 2004
  • This paper presents a method for real-time verification of Statecharts. Statecharts has been widely used for real-time reactive systems, and supports two time models: synchronous and asynchronous. However, existing real-time verification methods for them are incompatible with the asynchronous time model or increase state space by introducing new variables to the target models. We solved these problems by extending existing model checking algorithms. The extended algorithms can be used with both time models of Statecharts because they consider time increasing transitions only. In addition, they do not increase target state space since they count those transitions internally without additional variables. We extended an existing model checker, NuSMV, based on the proposed algorithms and conducted some experiments to show their advantage.

Formal Verification and Testing of RACE Protocol Using SMV (SMV를 이용한 RACE 프로토콜의 정형 검증 및 테스팅)

  • Nam, Won-Hong;Choe, Jin-Yeong;Han, U-Jong
    • Journal of the Institute of Electronics Engineers of Korea CI
    • /
    • v.39 no.3
    • /
    • pp.1-17
    • /
    • 2002
  • In this paper, we present our experiences in using symbolic model checker(SMV) to analyze a number of properties of RACE cache coherence protocol designed by ETRI(Electronics and Communications Research Institute) and to verify that RACE protocol satisfies important requirements. To investigate this, we specified the model of the RACE protocol as the input language of SMV and specified properties as a formula in temporal logic CTL. We successfully used the symbolic model checker to analyze a number of properties of RACE protocol. We verified that abnormal state/input combinations was not occurred and every possible request of processors was executed correctly We verified that RACE protocol satisfies liveness, safety and the property that any abnormal state/input combination was never occurred. Besides, We found some ambiguities of the specification and a case of starvation that the protocol designers could not expect before. By this verification experience, we show advantages of model checking method. And, we propose a new method to generate automatically test cases which are used in simulation and testing.