• Proceedings of the Korean Information Science Society Conference
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• 2001.04a
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• pp.541-543
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• 2001

일정 수준의 시스템 성능을 제공하기 위해 다수의 서버를 클러스터로 연결하여 동시에 가동할 경우, 서버의 가동 대수가 증가함으로 인해 발생하는 가용도 저하 문제를 해결해야 하며, 이를 위해서는 시스템의 성능 변화를 반영할 수 있는 가용 성능에 대한 명확한 정의가 요구된다. 본 논문에서는 비용 효율적인 결함허용을 위해 n 대의 주서버가 k 대의 여분서버로 구성된 클러스터 시스템에서 대기시간을 일정 수준이하로 만족시키는 새로운 가용도 척도에 근거한 최적 여분 서버 수를 계산하였다.

• Proceedings of the Korea Information Processing Society Conference
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• 2003.11a
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• pp.397-400
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• 2003

TMR(Triple Modular redundancy)은 공간여분(W/H 및 S/W)을 정적으로 활용하는 가장 간단한 구조를 지닌 대표적인 고장포용 기법중의 하나이다. TMR 구조 고장시 TMR 시스템 고장복구를 위해 잘못된 결과를 가지고 있는 프로그램의 일부분을 재실행 또는 프로그래밍 전체를 재시작하는 기법을 적용하는 것은 일반적으로 상당한 시간을 필요로 한다. 이러한 단점을 극복하기 위해 본 논문에서는 TMR 고장을 효과적으로 복구하기 위해 또 다른 형태의 시간여분 기법인 rollback과 rol1-forward 기법에 checkpoint들을 적용하여 처리하는 시간 및 공간여분을 혼용하는 기법을 제안하였다.

• The KIPS Transactions:PartA
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• v.13A no.5 s.102
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• pp.421-428
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• 2006

This paper proposes an integrated recovery approach applying retry and rollback techniques to recover the TMR failure. Combining the time redundancy techniques with W system is apparently effective to recover the TMR failure(or masked error) primarily caused by transient faults. These policies need fewer reconfigurations at the cost of extra time required for the time redundant schemes. The optimal numbers of retry and rollback to minimize the mean execution time of tasks are derived for the proposed method through computing the likelihoods of all possible states of the failed system. The effectiveness of the proposed method is validated through examining certain numerical examples and simulations conducted with a variety of parameters governing environmental characteristics.

• 전기의세계
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• v.46 no.9
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• pp.15-22
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• 1997

본 논문은 고장포용 시스템에서 고려되는 결함, 오류 및 고장의 개념과 특성을 살펴보고, 고장에 대한 강인성을 부가하기 위한 공간 여분(spatial redundancy) 및 시간 여분(time redundandy)을 바탕으로 다양한 고장포용의 설계 기법을 설명하며, 또한 고장포용 시스템의 성능을 평가하기 위한 다양한 기준중 확률적 접근방식에 바탕을 둔 신뢰도(reliability)와 가용성(availability), 그리고 유지성(maintainability)에 대해 설명한다. 또한, 고장포용기법의 연구용 목적으로 개발되어 일부는 실제 활용되고 있는 대표적인 고장포용 시스템들인 FTMP[3], STAR[4], SIEF[5], C.vmp[6] 등에 대해서 간단히 살펴보도록 하겠다.

• Journal of IKEEE
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• v.19 no.3
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• pp.378-384
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• 2015

In conventional HEVC inverse core transform architectures, extra $n{\times}n$ inverse transform block is added to $2n{\times}2n$ inverse transform block, and it operates as one $2n{\times}2n$ inverse transform block or two $n{\times}n$ inverse transform blocks. Thus, same number of pixels are processed in the same time, but it suffers from increased hardware size due to extra $n{\times}n$ inverse transform block. To avoid this problem, a novel $8{\times}8$ HEVC inverse core transform architecture was proposed to eliminate extra $4{\times}4$ inverse transform block based on multiplier reuse. This paper extends this approach and proposes a novel HEVC $16{\times}16$ inverse core transform architecture. Its frame processing time is same in $4{\times}4$, $8{\times}8$, and $16{\times}16$ inverse core transforms, and reduces gate counts by 13%.

• The Transactions of the Korea Information Processing Society
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• v.6 no.1
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• pp.216-224
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• 1999

In the paper we propose two recovery methods by adopting a rollback and/or roll-forward technique (S) to recover TMR failures in a TMR (structured ) system that is the simplest spatial redundancy. This technique is apparently effective to recovering TMR failures primarily caused by transient faults. The proposed policies carry out few reconfigurations at the cost of (minimal) time-overhead needed for those time-redundant schemes. The optimal checkpoint-interval vectors are derived for both methods through the likelihoods of all (possible) states of the system as well as the total execution-time. Consequently the effectiveness of our proposed policies is validated through certain numerical examples and simulations.

• Journal of the Korean Society of Safety
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• v.8 no.4
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• pp.201-206
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• 1993

A space-time finite element method was presented for time dependent problem. The method which treat both the space and time unformly were proposed and numerically tested. The weighted residual process was used to formulate a finite element method in a space-time domain based upon continuous Galerkin method. This method leads to a conditional stabie high-order accurate solver.

• Aerospace Engineering and Technology
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• v.3 no.1
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• pp.188-196
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• 2004

To optimize and limit the axial length of baffle in KSR-III engine, stability rating tests using pulse gun as one of artificial disturbance devices have been done. Decay time and other parameters for the evaluation of stabilization ability of engine to external perturbation have been analyzed to quantify stabilization capacity of engine, in other words, dynamic stability margin. If baffle does not cover flame zone enough which can be considered as collision region of injector, it wasn't be able to suppress external perturbation sufficiently. The limit of combustion stability margin of engine is assumed to be 50 mm length baffle.

• The KIPS Transactions:PartA
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• v.8A no.2
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• pp.81-90
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• 2001

As the rapid growth of Internet, computer systems are growing in its size and complexity. To meet high availability requirements for the systems, one usually uses both hardware and software fault tolerance techniques. To prevent failures of computer systems from software-aging phenomenon that come from long mission time, we adopt software rejuvenation method that stops and restarts the software in the servers intentionally. The method makes the systems clean and healthy state in which the probability of fault occurrence is very low. In this paper, we study how switchover time affects software rejuvenation of primary-backup server systems. Through experiments, we find that switchover time is an essential factor for deciding the rejuvenation policy.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.5
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• pp.7-16
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• 2000

This paper described a design and implementation of the division/square-root for a redundant floating point binary number using high-speed quotient selector. This division/square-root used the method of a redundant binary addition with 25MHz clock speed. The addition of two numbers can be performed in a constant time independent of the word length since carry propagation can be eliminated. We have developed a 16-bit VLSI circuit for division and square-root operations used extensively in each iterative step. It performed the division and square-toot by a redundant binary addition to the shifted binary number every 16 cycles. Also the circuit uses the nonrestoring method to obtain a quotient. The quotient selection logic used a leading three digits of partial remainders in order to be implemented in a simple circuit. As a result, the performance of the proposed scheme is further enhanced in the speed of operation process by applying new quotient selection addition logic which can be parallelly process the quotient decision field. It showed the speed-up of 13% faster than previously presented schemes used the same algorithms.